diff --git a/LICENSE b/LICENSE index 88190f1f55..78875df735 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2000-2008 The Regents of The University of Michigan +Copyright (c) 2000-2011 The Regents of The University of Michigan All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/README b/README index f8eef7417d..3b6a3f6bd9 100644 --- a/README +++ b/README @@ -1,4 +1,4 @@ -This is release 2.0_beta6 of the M5 simulator. +This is the M5 simulator. For detailed information about building the simulator and getting started please refer to http://www.m5sim.org. @@ -9,13 +9,16 @@ http://www.m5sim.org/wiki/index.php/Running_M5 Short version: -1. If you don't have SCons version 0.96.91 or newer, get it from +1. If you don't have SCons version 0.98.1 or newer, get it from http://wwww.scons.org. -2. If you don't have SWIG version 1.3.28 or newer, get it from +2. If you don't have SWIG version 1.3.31 or newer, get it from http://wwww.swig.org. -3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This +3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer +(the dev version with header files), zlib, and the m4 preprocessor. + +4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This will build the debug version of the m5 binary (m5.debug) for the Alpha syscall emulation target, and run the quick regression tests on it. @@ -25,18 +28,21 @@ WHAT'S INCLUDED (AND NOT) ------------------------- The basic source release includes these subdirectories: - - m5: - - src: source code of the m5 simulator - - tests: regression tests + - m5: + - configs: simulation configuration scripts - ext: less-common external packages needed to build m5 + - src: source code of the m5 simulator + - system: source for some optional system software for simulated systems + - tests: regression tests + - util: useful utility programs and files -To run full-system simulations, you will need compiled console, -PALcode, and kernel binaries and one or more disk images. These files -are collected in a separate archive, m5_system.tar.bz2. This file -can he downloaded separately. +To run full-system simulations, you will need compiled system firmware +(console and PALcode for Alpha), kernel binaries and one or more disk images. +These files for Alpha are collected in a separate archive, m5_system.tar.bz2. +This file can he downloaded separately. -M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP -Tru64 version of Unix. We are able to distribute Linux and FreeBSD -bootdisks, but we are unable to distribute bootable disk images of +Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the +proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux +and FreeBSD bootdisks, but we are unable to distribute bootable disk images of Tru64 Unix. If you have a Tru64 license and are interested in obtaining disk images, contact us at m5-users@m5sim.org diff --git a/RELEASE_NOTES b/RELEASE_NOTES deleted file mode 100644 index f10ffddae6..0000000000 --- a/RELEASE_NOTES +++ /dev/null @@ -1,149 +0,0 @@ -October 6, 2008: m5_2.0_beta6 --------------------- -New Features -1. Support for gcc 4.3 -2. Core m5 code in libm5 for integration with other simulators -3. Preliminary support for X86 SE mode -4. Additional system calls emulated -5. m5term updated to work on OS X -6. Ability to disable listen sockets -7. Event queue performance improvements and rewrite -8. Better errors for unconnected memory ports - -Bug fixes -1. ALPHA_SE O3 perlbmk benchmark -2. Translation bug where O3 could fetch from uncachable memory -3. Many minor bugs - -Outstanding issues for 2.0 release: --------------------- -1. Statistics cleanup -2. Improve regression system -3. Testing -4. Validation - -March 1, 2008: m5_2.0_beta5 --------------------- -New Features -1. Rick Strong's Simpoints config changes -2. Support for FSU ARM port -3. EXTRAS= option allow architectures to be specified - -Bug fixes -1. Bus timing more realistic -2. Cache writeback, LL/SC fixes -3. Minor IGbE NIC fixes -4. O3 op latency fix -5. SPARC TLB demap fixes -6. SPARC SE memory layout fixes -7. Variety of MIPS fixes - -Nov 4, 2007: m5_2.0_beta4 --------------------- -New Features -1. New cache model -2. Use of a I/O cache between devices and memory -3. Ability to include compiled code with EXTRAS= -4. Python creation of params structures for initialization -5. Ability to remotely debug in SE - -Bug fixes: -1. Fix SE serialization -2. SPARC_FS booting with TimingSimpleCPU -3. Rename cycles() to ticks() -4. Various SPARC ISA fixes -5. Draining code for checkpointing -6. Various performance improvements - -Possible Incompatibilities: -1. Real TLBs are now used in SE mode. This is more accurate however it could - cause some problems if you've modified the way page handling is done in - SE mode. -2. There have been many changes to the way the SCons files work. SimObjects, - sources files, and trace flags are all specified in the SConscript files. - To see how to add your sources take a look at one of them. -3. Python is now used to created the parameter structs that were created - manually before. The parameters listed in a py file are turned into - a header file with the same name (e.g. BadDevice.py -> BadDevice.hh). - With this change the structs can be populated automatically and the - ugly macros to define and create SimObjects at the bottem of source - files are gone. The parameter structs also automatically inherit - parameters from their parents. - -May 16, 2007: m5_2.0_beta3 --------------------- -New Features -1. Some support for SPARC full-system simulation -2. Reworking of trace facitities (parameter names changed, variadic macros - removed) -3. Scons script cleanups -4. Some support for compiling with Intel CC - -Bug fixes since beta 2: -1. Many SPARC linux syscall emulation support fixes -2. Multiprocessor linux boot using the detailed O3 CPU module -3. Workaround for DMA bug (final solution to be released with 2.0f) -4. Simulator performance and memory leak fixes -5. Fixed issue where console could stop printing in ALPHA_FS -6. Fix issues with remote debugging -7. Several compile fixes, including gcc 4.1 -8. Many other minor fixes and enhancements - -Nov. 28, 2006: m5_2.0_beta2 --------------------- -Bug fixes since beta 1: -1. Many cache issues resolved -2. Uni-coherence fixes in full-system -3. LL/SC Support -4. Draining/Switchover -5. Functional Accesses -6. Bus now has real timing -7. Single config file for all SpecCPU2000 benchmarks -8. Several other minor bug fixes and enhancements - -Aug. 25, 2006: m5_2.0_beta patch 1 --------------------- -Handful of minor bug fixes for m5_2.0_beta, -along with a few new regression tests. - -Aug. 15, 2006: m5_2.0_beta --------------------- -Major update to M5 including: -- New CPU model -- New memory system -- More extensive python integration -- Preliminary syscall emulation support for MIPS and SPARC -This is a *beta* release, meaning that some features are not complete, -and some features from M5 1.X aren't currently supported (e.g., MP -coherence). We are working to address these limitations and hope to -have a complete 2.0 release soon. - -Oct. 8, 2005: m5_1.1 --------------------- -Update release for IOSCA workshop mini-tutorial. New features include: -- Preliminary FreeBSD support -- Integration of regression tests into scons build framework -- Several bug fixes and better compatibility for Cygwin hosts -- Major cleanup of Alpha system code (console, PAL, etc.) to make - it easier for others to build/modify -- Fixes to enable compilation under g++ 4.0 -- Numerous minor bug fixes - -June 10, 2005: m5_1.0_web -------------------------- -The 1.0 release posted on Sourceforge after the ISCA tutorial contains -just a few very minor fixes relative to the CD. - -June 5, 2005: m5_1.0_tutorial ------------------------------ -First non-beta release. This release was on the CD distributed at the -ISCA tutorial. Major enhancements relative to beta releases include -Linux support and Python-based configuration language. - -June 17, 2004: m5_1.0_beta2 ---------------------------- -Stealth-mode beta bug-fix update, not widely advertised. - -Oct. 17, 2003: m5_1.0_beta1 ---------------------------- -Early beta release. diff --git a/src/SConscript b/src/SConscript index cad0736c54..0ee1447476 100755 --- a/src/SConscript +++ b/src/SConscript @@ -446,7 +446,7 @@ def makeInfoPyFile(target, source, env): # Generate a file that wraps the basic top level files env.Command('python/m5/info.py', - [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], + [ '#/AUTHORS', '#/LICENSE', '#/README', ], MakeAction(makeInfoPyFile, Transform("INFO"))) PySource('m5', 'python/m5/info.py') diff --git a/src/arch/generic/debugfaults.hh b/src/arch/generic/debugfaults.hh new file mode 100644 index 0000000000..acffadc343 --- /dev/null +++ b/src/arch/generic/debugfaults.hh @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2010 Advanced Micro Devices + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_GENERIC_DEBUGFAULTS_HH__ +#define __ARCH_GENERIC_DEBUGFAULTS_HH__ + +#include "base/misc.hh" +#include "sim/faults.hh" + +#include + +namespace GenericISA +{ +class M5DebugFault : public FaultBase +{ + public: + enum DebugFunc + { + PanicFunc, + FatalFunc, + WarnFunc, + WarnOnceFunc + }; + + protected: + std::string message; + DebugFunc func; + + public: + M5DebugFault(DebugFunc _func, std::string _message) : + message(_message), func(_func) + {} + + FaultName + name() const + { + switch (func) { + case PanicFunc: + return "panic fault"; + case FatalFunc: + return "fatal fault"; + case WarnFunc: + return "warn fault"; + case WarnOnceFunc: + return "warn_once fault"; + default: + panic("unrecognized debug function number\n"); + } + } + + void + invoke(ThreadContext *tc, + StaticInstPtr inst = StaticInst::nullStaticInstPtr) + { + switch (func) { + case PanicFunc: + panic(message); + break; + case FatalFunc: + fatal(message); + break; + case WarnFunc: + warn(message); + break; + case WarnOnceFunc: + warn_once(message); + break; + default: + panic("unrecognized debug function number\n"); + } + } +}; +} // namespace GenericISA + +#endif // __ARCH_GENERIC_DEBUGFAULTS_HH__ diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 27de9da11a..9cb7746475 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -46,6 +46,7 @@ if env['TARGET_ISA'] == 'x86': Source('cpuid.cc') Source('emulenv.cc') Source('faults.cc') + Source('insts/badmicroop.cc') Source('insts/microfpop.cc') Source('insts/microldstop.cc') Source('insts/micromediaop.cc') diff --git a/src/arch/x86/insts/badmicroop.cc b/src/arch/x86/insts/badmicroop.cc new file mode 100644 index 0000000000..ef493f250d --- /dev/null +++ b/src/arch/x86/insts/badmicroop.cc @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2011 Advanced Micro Devices + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/insts/badmicroop.hh" +#include "arch/x86/isa_traits.hh" +#include "arch/x86/decoder.hh" + +namespace X86ISA +{ + +// This microop needs to be allocated on the heap even though it could +// theoretically be statically allocated. The reference counted pointer would +// try to delete the static memory when it was destructed. +const StaticInstPtr badMicroop = + new X86ISAInst::MicroPanic(NoopMachInst, "BAD", + StaticInst::IsMicroop | StaticInst::IsLastMicroop, + "Invalid microop!", 0); + +} // namespace X86ISA diff --git a/src/arch/x86/insts/badmicroop.hh b/src/arch/x86/insts/badmicroop.hh new file mode 100644 index 0000000000..57fe242c49 --- /dev/null +++ b/src/arch/x86/insts/badmicroop.hh @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2011 Advanced Micro Devices + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_INSTS_BADMICROOP_HH__ +#define __ARCH_X86_INSTS_BADMICROOP_HH__ + +class StaticInstPtr; + +namespace X86ISA +{ + +extern const StaticInstPtr badMicroop; + +} // namespace X86ISA + +#endif //__ARCH_X86_INSTS_BADMICROOP_HH__ diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh index fcf051a371..4f4176b770 100644 --- a/src/arch/x86/insts/macroop.hh +++ b/src/arch/x86/insts/macroop.hh @@ -41,6 +41,7 @@ #define __ARCH_X86_INSTS_MACROOP_HH__ #include "arch/x86/emulenv.hh" +#include "arch/x86/insts/badmicroop.hh" #include "arch/x86/types.hh" #include "arch/x86/insts/static_inst.hh" @@ -76,8 +77,10 @@ class MacroopBase : public X86StaticInst StaticInstPtr fetchMicroop(MicroPC microPC) const { - assert(microPC < numMicroops); - return microops[microPC]; + if (microPC >= numMicroops) + return badMicroop; + else + return microops[microPC]; } std::string diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index 6aee874493..dedea0f3d6 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -50,9 +50,6 @@ namespace X86ISA bool subtract) const { DPRINTF(X86, "flagMask = %#x\n", flagMask); - if (_destRegIdx[0] & IntFoldBit) { - _dest >>= 8; - } uint64_t flags = oldFlags & ~flagMask; if(flagMask & (ECFBit | CFBit)) { diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 58b1fbc626..674e69e982 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -53,6 +53,7 @@ output header {{ #include #include +#include "arch/generic/debugfaults.hh" #include "arch/x86/emulenv.hh" #include "arch/x86/insts/macroop.hh" #include "arch/x86/insts/microfpop.hh" @@ -113,6 +114,7 @@ output exec {{ #include "arch/x86/regs/misc.hh" #include "arch/x86/tlb.hh" #include "base/bigint.hh" +#include "base/compiler.hh" #include "base/condcodes.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index 4b2ecdd5aa..220c1af972 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -45,16 +45,29 @@ output header {{ class MicroDebugBase : public X86ISA::X86MicroopBase { protected: + typedef GenericISA::M5DebugFault::DebugFunc DebugFunc; + DebugFunc func; std::string message; uint8_t cc; public: - MicroDebugBase(ExtMachInst _machInst, const char * mnem, + MicroDebugBase(ExtMachInst machInst, const char * mnem, const char * instMnem, uint64_t setFlags, - std::string _message, uint8_t _cc); + DebugFunc _func, std::string _message, uint8_t _cc) : + X86MicroopBase(machInst, mnem, instMnem, setFlags, No_OpClass), + func(_func), message(_message), cc(_cc) + {} - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + response << "\"" << message << "\""; + + return response.str(); + } }; }}; @@ -70,53 +83,31 @@ def template MicroDebugDeclare {{ }}; def template MicroDebugExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Fault + %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { %(op_decl)s %(op_rd)s if (%(cond_test)s) { - %(func)s("%s\n", message); + return new GenericISA::M5DebugFault(func, message); + } else { + return NoFault; } - return NoFault; } }}; -output decoder {{ - inline MicroDebugBase::MicroDebugBase( - ExtMachInst machInst, const char * mnem, const char * instMnem, - uint64_t setFlags, std::string _message, uint8_t _cc) : - X86MicroopBase(machInst, mnem, instMnem, - setFlags, No_OpClass), - message(_message), cc(_cc) - { - } -}}; - def template MicroDebugConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, std::string _message, uint8_t _cc) : %(base_class)s(machInst, "%(func)s", instMnem, - setFlags, _message, _cc) + setFlags, %(func_num)s, _message, _cc) { %(constructor)s; } }}; -output decoder {{ - std::string MicroDebugBase::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - printMnemonic(response, instMnem, mnemonic); - response << "\"" << message << "\""; - - return response.str(); - } -}}; - let {{ class MicroDebug(X86Microop): def __init__(self, message, flags=None): @@ -142,13 +133,14 @@ let {{ header_output = "" decoder_output = "" - def buildDebugMicro(func): + def buildDebugMicro(func, func_num): global exec_output, header_output, decoder_output iop = InstObjParams(func, "Micro%sFlags" % func.capitalize(), "MicroDebugBase", {"code": "", "func": func, + "func_num": "GenericISA::M5DebugFault::%s" % func_num, "cond_test": "checkCondition(ccFlagBits, cc)"}) exec_output += MicroDebugExecute.subst(iop) header_output += MicroDebugDeclare.subst(iop) @@ -158,6 +150,7 @@ let {{ "MicroDebugBase", {"code": "", "func": func, + "func_num": "GenericISA::M5DebugFault::%s" % func_num, "cond_test": "true"}) exec_output += MicroDebugExecute.subst(iop) header_output += MicroDebugDeclare.subst(iop) @@ -169,8 +162,8 @@ let {{ global microopClasses microopClasses[func] = MicroDebugChild - buildDebugMicro("panic") - buildDebugMicro("fatal") - buildDebugMicro("warn") - buildDebugMicro("warn_once") + buildDebugMicro("panic", "PanicFunc") + buildDebugMicro("fatal", "FatalFunc") + buildDebugMicro("warn", "WarnFunc") + buildDebugMicro("warn_once", "WarnOnceFunc") }}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 216a74c6cb..cd649d6447 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -301,6 +301,46 @@ let {{ "dataSize" : self.dataSize, "addressSize" : self.addressSize, "memFlags" : self.memFlags} return allocator + + class BigLdStOp(X86Microop): + def __init__(self, data, segment, addr, disp, + dataSize, addressSize, baseFlags, atCPL0, prefetch): + self.data = data + [self.scale, self.index, self.base] = addr + self.disp = disp + self.segment = segment + self.dataSize = dataSize + self.addressSize = addressSize + self.memFlags = baseFlags + if atCPL0: + self.memFlags += " | (CPL0FlagBit << FlagShift)" + if prefetch: + self.memFlags += " | Request::PREFETCH" + self.memFlags += " | (machInst.legacy.addr ? " + \ + "(AddrSizeFlagBit << FlagShift) : 0)" + + def getAllocator(self, microFlags): + allocString = ''' + (%(dataSize)s >= 4) ? + (StaticInstPtr)(new %(class_name)sBig(machInst, + macrocodeBlock, %(flags)s, %(scale)s, %(index)s, + %(base)s, %(disp)s, %(segment)s, %(data)s, + %(dataSize)s, %(addressSize)s, %(memFlags)s)) : + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s, %(scale)s, %(index)s, + %(base)s, %(disp)s, %(segment)s, %(data)s, + %(dataSize)s, %(addressSize)s, %(memFlags)s)) + ''' + allocator = allocString % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "scale" : self.scale, "index" : self.index, + "base" : self.base, + "disp" : self.disp, + "segment" : self.segment, "data" : self.data, + "dataSize" : self.dataSize, "addressSize" : self.addressSize, + "memFlags" : self.memFlags} + return allocator }}; let {{ @@ -315,7 +355,8 @@ let {{ EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); ''' - def defineMicroLoadOp(mnemonic, code, mem_flags="0"): + def defineMicroLoadOp(mnemonic, code, bigCode='', + mem_flags="0", big=True): global header_output global decoder_output global exec_output @@ -324,16 +365,22 @@ let {{ name = mnemonic.lower() # Build up the all register version of this micro op - iop = InstObjParams(name, Name, 'X86ISA::LdStOp', - {"code": code, - "ea_code": calculateEA}) - header_output += MicroLdStOpDeclare.subst(iop) - decoder_output += MicroLdStOpConstructor.subst(iop) - exec_output += MicroLoadExecute.subst(iop) - exec_output += MicroLoadInitiateAcc.subst(iop) - exec_output += MicroLoadCompleteAcc.subst(iop) + iops = [InstObjParams(name, Name, 'X86ISA::LdStOp', + {"code": code, "ea_code": calculateEA})] + if big: + iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp', + {"code": bigCode, "ea_code": calculateEA})] + for iop in iops: + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLoadExecute.subst(iop) + exec_output += MicroLoadInitiateAcc.subst(iop) + exec_output += MicroLoadCompleteAcc.subst(iop) - class LoadOp(LdStOp): + base = LdStOp + if big: + base = BigLdStOp + class LoadOp(base): def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", @@ -346,12 +393,15 @@ let {{ microopClasses[name] = LoadOp - defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') + defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', + 'Data = Mem & mask(dataSize * 8);') defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', - '(StoreCheck << FlagShift)') + 'Data = Mem & mask(dataSize * 8);', + '(StoreCheck << FlagShift)') defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', - '(StoreCheck << FlagShift) | Request::LOCKED') - defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') + 'Data = Mem & mask(dataSize * 8);', + '(StoreCheck << FlagShift) | Request::LOCKED') + defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False) def defineMicroStoreOp(mnemonic, code, \ postCode="", completeCode="", mem_flags="0"): diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index 2871d5a892..ac78b090dd 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -114,8 +114,16 @@ let {{ self.dataSize = dataSize def getAllocator(self, microFlags): - allocator = '''new %(class_name)s(machInst, macrocodeBlock, - %(flags)s, %(dest)s, %(imm)s, %(dataSize)s)''' % { + allocString = ''' + (%(dataSize)s >= 4) ? + (StaticInstPtr)(new %(class_name)sBig(machInst, + macrocodeBlock, %(flags)s, %(dest)s, %(imm)s, + %(dataSize)s)) : + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s, %(dest)s, %(imm)s, + %(dataSize)s)) + ''' + allocator = allocString % { "class_name" : self.className, "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), @@ -152,12 +160,15 @@ let {{ let {{ # Build up the all register version of this micro op - iop = InstObjParams("limm", "Limm", 'X86MicroopBase', - {"code" : "DestReg = merge(DestReg, imm, dataSize);"}) - header_output += MicroLimmOpDeclare.subst(iop) - decoder_output += MicroLimmOpConstructor.subst(iop) - decoder_output += MicroLimmOpDisassembly.subst(iop) - exec_output += MicroLimmOpExecute.subst(iop) + iops = [InstObjParams("limm", "Limm", 'X86MicroopBase', + {"code" : "DestReg = merge(DestReg, imm, dataSize);"}), + InstObjParams("limm", "LimmBig", 'X86MicroopBase', + {"code" : "DestReg = imm & mask(dataSize * 8);"})] + for iop in iops: + header_output += MicroLimmOpDeclare.subst(iop) + decoder_output += MicroLimmOpConstructor.subst(iop) + decoder_output += MicroLimmOpDisassembly.subst(iop) + exec_output += MicroLimmOpExecute.subst(iop) iop = InstObjParams("lfpimm", "Lfpimm", 'X86MicroopBase', {"code" : "FpDestReg.uqw = imm"}) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index ccfcb3a69a..e2a51c1271 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -51,6 +51,8 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; + IntReg result M5_VAR_USED; + if(%(cond_check)s) { %(code)s; @@ -79,6 +81,8 @@ def template MicroRegOpImmExecute {{ %(op_decl)s; %(op_rd)s; + IntReg result M5_VAR_USED; + if(%(cond_check)s) { %(code)s; @@ -224,8 +228,8 @@ let {{ MicroRegOpExecute) class RegOpMeta(type): - def buildCppClasses(self, name, Name, suffix, \ - code, flag_code, cond_check, else_code, cond_control_flag_init): + def buildCppClasses(self, name, Name, suffix, code, big_code, \ + flag_code, cond_check, else_code, cond_control_flag_init): # Globals to stick the output in global header_output @@ -235,11 +239,13 @@ let {{ # Stick all the code together so it can be searched at once allCode = "|".join((code, flag_code, cond_check, else_code, cond_control_flag_init)) + allBigCode = "|".join((big_code, flag_code, cond_check, else_code, + cond_control_flag_init)) # If op2 is used anywhere, make register and immediate versions # of this code. matcher = re.compile("(?s?)op2(?P\\.\\w+)?") - match = matcher.search(allCode) + match = matcher.search(allCode + allBigCode) if match: typeQual = "" if match.group("typeQual"): @@ -247,6 +253,7 @@ let {{ src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) self.buildCppClasses(name, Name, suffix, matcher.sub(src2_name, code), + matcher.sub(src2_name, big_code), matcher.sub(src2_name, flag_code), matcher.sub(src2_name, cond_check), matcher.sub(src2_name, else_code), @@ -254,6 +261,7 @@ let {{ imm_name = "%simm8" % match.group("prefix") self.buildCppClasses(name + "i", Name, suffix + "Imm", matcher.sub(imm_name, code), + matcher.sub(imm_name, big_code), matcher.sub(imm_name, flag_code), matcher.sub(imm_name, cond_check), matcher.sub(imm_name, else_code), @@ -264,27 +272,32 @@ let {{ # a version without it and fix up this version to use it. if flag_code != "" or cond_check != "true": self.buildCppClasses(name, Name, suffix, - code, "", "true", else_code, "") + code, big_code, "", "true", else_code, "") suffix = "Flags" + suffix # If psrc1 or psrc2 is used, we need to actually insert code to # compute it. - matcher = re.compile("(?= 4) ? + (StaticInstPtr)(new %(class_name)sBig(machInst, + macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, + %(dest)s, %(dataSize)s, %(ext)s)) : + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, + %(dest)s, %(dataSize)s, %(ext)s)) + ''' + allocator = allocString % { + "class_name" : className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "op2" : self.op2, + "dest" : self.dest, + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator + else: + className = self.className + if self.mnemonic == self.base_mnemonic + 'i': + className += "Imm" + allocator = '''new %(class_name)s(machInst, macrocodeBlock, + %(flags)s, %(src1)s, %(op2)s, %(dest)s, + %(dataSize)s, %(ext)s)''' % { + "class_name" : className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "op2" : self.op2, + "dest" : self.dest, + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator class LogicRegOp(RegOp): abstract = True flag_code = ''' //Don't have genFlags handle the OF or CF bits uint64_t mask = CFBit | ECFBit | OFBit; - ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2); //If a logic microop wants to set these, it wants to set them to 0. ccFlagBits &= ~(CFBit & ext); ccFlagBits &= ~(ECFBit & ext); @@ -401,12 +448,12 @@ let {{ class FlagRegOp(RegOp): abstract = True flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" class SubRegOp(RegOp): abstract = True flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" class CondRegOp(RegOp): abstract = True @@ -428,31 +475,44 @@ let {{ src1, src2, flags, dataSize) class Add(FlagRegOp): - code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' + code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' + big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' class Or(LogicRegOp): - code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' + code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' + big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' class Adc(FlagRegOp): code = ''' CCFlagBits flags = ccFlagBits; - DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); + DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); + ''' + big_code = ''' + CCFlagBits flags = ccFlagBits; + DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); ''' class Sbb(SubRegOp): code = ''' CCFlagBits flags = ccFlagBits; - DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); + DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); + ''' + big_code = ''' + CCFlagBits flags = ccFlagBits; + DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); ''' class And(LogicRegOp): - code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' + code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' + big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' class Sub(SubRegOp): - code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' + code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' + big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' class Xor(LogicRegOp): - code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' + code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' + big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' class Mul1s(WrRegOp): code = ''' @@ -505,6 +565,7 @@ let {{ class Mulel(RdRegOp): code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' + big_code = 'DestReg = ProdLow & mask(dataSize * 8);' class Muleh(RdRegOp): def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): @@ -513,6 +574,7 @@ let {{ super(RdRegOp, self).__init__(dest, src1, \ "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' + big_code = 'DestReg = ProdHi & mask(dataSize * 8);' # One or two bit divide class Div1(WrRegOp): @@ -540,7 +602,7 @@ let {{ # Step divide class Div2(RegOp): - code = ''' + divCode = ''' uint64_t dividend = Remainder; uint64_t divisor = Divisor; uint64_t quotient = Quotient; @@ -587,11 +649,13 @@ let {{ } } //Keep track of how many bits there are still to pull in. - DestReg = merge(DestReg, remaining, dataSize); + %s //Record the final results Remainder = remainder; Quotient = quotient; ''' + code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" + big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" flag_code = ''' if (remaining == 0) ccFlagBits = ccFlagBits | (ext & EZFBit); @@ -601,9 +665,11 @@ let {{ class Divq(RdRegOp): code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' + big_code = 'DestReg = Quotient & mask(dataSize * 8);' class Divr(RdRegOp): code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' + big_code = 'DestReg = Remainder & mask(dataSize * 8);' class Mov(CondRegOp): code = 'DestReg = merge(SrcReg1, op2, dataSize)' @@ -616,6 +682,10 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); ''' + big_code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); + ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -641,14 +711,19 @@ let {{ ''' class Srl(RegOp): + # Because what happens to the bits shift -in- on a right shift + # is not defined in the C/C++ standard, we have to mask them out + # to be sure they're zero. code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); - // Because what happens to the bits shift -in- on a right shift - // is not defined in the C/C++ standard, we have to mask them out - // to be sure they're zero. uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); ''' + big_code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); + DestReg = (psrc1 >> shiftAmt) & logicalMask; + ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -671,15 +746,21 @@ let {{ ''' class Sra(RegOp): + # Because what happens to the bits shift -in- on a right shift + # is not defined in the C/C++ standard, we have to sign extend + # them manually to be sure. code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); - // Because what happens to the bits shift -in- on a right shift - // is not defined in the C/C++ standard, we have to sign extend - // them manually to be sure. uint64_t arithMask = (shiftAmt == 0) ? 0 : -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); ''' + big_code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + uint64_t arithMask = (shiftAmt == 0) ? 0 : + -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); + DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); + ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -704,13 +785,11 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8); - if(realShiftAmt) - { + if (realShiftAmt) { uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -739,16 +818,14 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); - if(realShiftAmt) - { + if (realShiftAmt) { CCFlagBits flags = ccFlagBits; uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); if (realShiftAmt > 1) top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -780,14 +857,12 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8); - if(realShiftAmt) - { + if (realShiftAmt) { uint64_t top = psrc1 << realShiftAmt; uint64_t bottom = bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -816,8 +891,7 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); - if(realShiftAmt) - { + if (realShiftAmt) { CCFlagBits flags = ccFlagBits; uint64_t top = psrc1 << realShiftAmt; uint64_t bottom = flags.cf << (realShiftAmt - 1); @@ -826,8 +900,7 @@ let {{ bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt + 1); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -853,10 +926,10 @@ let {{ ''' class Sld(RegOp): - code = ''' + sldCode = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t dataBits = dataSize * 8; - uint8_t realShiftAmt = shiftAmt % (2 * dataBits); + uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); uint64_t result; if (realShiftAmt == 0) { result = psrc1; @@ -867,8 +940,10 @@ let {{ result = (DoubleBits << (realShiftAmt - dataBits)) | (psrc1 >> (2 * dataBits - realShiftAmt)); } - DestReg = merge(DestReg, result, dataSize); + %s ''' + code = sldCode % "DestReg = merge(DestReg, result, dataSize);" + big_code = sldCode % "DestReg = result & mask(dataSize * 8);" flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -899,10 +974,10 @@ let {{ ''' class Srd(RegOp): - code = ''' + srdCode = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t dataBits = dataSize * 8; - uint8_t realShiftAmt = shiftAmt % (2 * dataBits); + uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); uint64_t result; if (realShiftAmt == 0) { result = psrc1; @@ -919,8 +994,10 @@ let {{ logicalMask) | (psrc1 << (2 * dataBits - realShiftAmt)); } - DestReg = merge(DestReg, result, dataSize); + %s ''' + code = srdCode % "DestReg = merge(DestReg, result, dataSize);" + big_code = srdCode % "DestReg = result & mask(dataSize * 8);" flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -986,6 +1063,12 @@ let {{ ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); ''' + big_code = ''' + int flag = bits(ccFlagBits, imm8); + DestReg = flag & mask(dataSize * 8); + ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : + (ccFlagBits & ~EZFBit); + ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Ruflag, self).__init__(dest, \ @@ -1000,6 +1083,14 @@ let {{ ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); ''' + big_code = ''' + MiscReg flagMask = 0x3F7FDD5; + MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; + int flag = bits(flags, imm8); + DestReg = flag & mask(dataSize * 8); + ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : + (ccFlagBits & ~EZFBit); + ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Rflag, self).__init__(dest, \ @@ -1015,6 +1106,15 @@ let {{ val = sign_bit ? (val | ~maskVal) : (val & maskVal); DestReg = merge(DestReg, val, dataSize); ''' + big_code = ''' + IntReg val = psrc1; + // Mask the bit position so that it wraps. + int bitPos = op2 & (dataSize * 8 - 1); + int sign_bit = bits(val, bitPos, bitPos); + uint64_t maskVal = mask(bitPos+1); + val = sign_bit ? (val | ~maskVal) : (val & maskVal); + DestReg = val & mask(dataSize * 8); + ''' flag_code = ''' if (!sign_bit) ccFlagBits = ccFlagBits & @@ -1026,12 +1126,13 @@ let {{ class Zext(RegOp): code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' + big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' class Rddr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rddr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) - code = ''' + rdrCode = ''' CR4 cr4 = CR4Op; DR7 dr7 = DR7Op; if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { @@ -1039,9 +1140,11 @@ let {{ } else if (dr7.gd) { fault = new DebugException(); } else { - DestReg = merge(DestReg, DebugSrc1, dataSize); + %s } ''' + code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" + big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" class Wrdr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): @@ -1066,13 +1169,15 @@ let {{ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rdcr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) - code = ''' + rdcrCode = ''' if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = new InvalidOpcode(); } else { - DestReg = merge(DestReg, ControlSrc1, dataSize); + %s } ''' + code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" + big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" class Wrcr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): @@ -1154,24 +1259,20 @@ let {{ ''' class Rdbase(SegOp): - code = ''' - DestReg = merge(DestReg, SegBaseSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' + big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' class Rdlimit(SegOp): - code = ''' - DestReg = merge(DestReg, SegLimitSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' + big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' class RdAttr(SegOp): - code = ''' - DestReg = merge(DestReg, SegAttrSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' + big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' class Rdsel(SegOp): - code = ''' - DestReg = merge(DestReg, SegSelSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' + big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' class Rdval(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): diff --git a/src/arch/x86/microcode_rom.hh b/src/arch/x86/microcode_rom.hh index f8ad410ce4..84c503bb9f 100644 --- a/src/arch/x86/microcode_rom.hh +++ b/src/arch/x86/microcode_rom.hh @@ -32,6 +32,7 @@ #define __ARCH_X86_MICROCODE_ROM_HH__ #include "arch/x86/emulenv.hh" +#include "arch/x86/insts/badmicroop.hh" #include "cpu/static_inst.hh" namespace X86ISAInst @@ -60,8 +61,10 @@ namespace X86ISAInst fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop) { microPC = normalMicroPC(microPC); - assert(microPC < numMicroops); - return genFuncs[microPC](curMacroop); + if (microPC >= numMicroops) + return X86ISA::badMicroop; + else + return genFuncs[microPC](curMacroop); } }; } diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index c06ec18bcc..5c67e28e19 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -225,7 +225,11 @@ namespace X86ISA { assert(emiIsReady); emiIsReady = false; - nextPC.npc(nextPC.pc() + getInstSize()); + if (!nextPC.size()) { + Addr size = getInstSize(); + nextPC.size(size); + nextPC.npc(nextPC.pc() + size); + } return emi; } }; diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 5a208446a5..4641141d35 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -222,7 +222,61 @@ namespace X86ISA return true; } - typedef GenericISA::UPCState PCState; + class PCState : public GenericISA::UPCState + { + protected: + typedef GenericISA::UPCState Base; + + uint8_t _size; + + public: + void + set(Addr val) + { + Base::set(val); + _size = 0; + } + + PCState() {} + PCState(Addr val) { set(val); } + + uint8_t size() const { return _size; } + void size(uint8_t newSize) { _size = newSize; } + + bool + branching() const + { + return this->npc() != this->pc() + size(); + } + + void + advance() + { + Base::advance(); + _size = 0; + } + + void + uEnd() + { + Base::uEnd(); + _size = 0; + } + + void + serialize(std::ostream &os) + { + Base::serialize(os); + SERIALIZE_SCALAR(_size); + } + + void + unserialize(Checkpoint *cp, const std::string §ion) + { + Base::unserialize(cp, section); + UNSERIALIZE_SCALAR(_size); + } + }; struct CoreSpecific { int core_type; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 2e4e4819e9..d2cde496e5 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1070,6 +1070,8 @@ DefaultFetch::fetch(bool &status_change) Addr pcOffset = fetchOffset[tid]; Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; + bool inRom = isRomMicroPC(thisPC.microPC()); + // If returning from the delay of a cache miss, then update the status // to running, otherwise do the cache access. Possibly move this up // to tick() function. @@ -1083,7 +1085,7 @@ DefaultFetch::fetch(bool &status_change) Addr block_PC = icacheBlockAlignPC(fetchAddr); // Unless buffer already got the block, fetch it from icache. - if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid]) { + if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) { DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " "instruction, starting at PC %s.\n", tid, thisPC); @@ -1155,7 +1157,7 @@ DefaultFetch::fetch(bool &status_change) !predictedBranch) { // If we need to process more memory, do it now. - if (!curMacroop && !predecoder.extMachInstReady()) { + if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) { if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { // Walk past any annulled delay slot instructions. Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; @@ -1181,7 +1183,7 @@ DefaultFetch::fetch(bool &status_change) // Extract as many instructions and/or microops as we can from // the memory we've processed so far. do { - if (!curMacroop) { + if (!(curMacroop || inRom)) { if (predecoder.extMachInstReady()) { ExtMachInst extMachInst; @@ -1202,8 +1204,13 @@ DefaultFetch::fetch(bool &status_change) break; } } - if (curMacroop) { - staticInst = curMacroop->fetchMicroop(thisPC.microPC()); + if (curMacroop || inRom) { + if (inRom) { + staticInst = cpu->microcodeRom.fetchMicroop( + thisPC.microPC(), curMacroop); + } else { + staticInst = curMacroop->fetchMicroop(thisPC.microPC()); + } if (staticInst->isLastMicroop()) { curMacroop = NULL; pcOffset = 0; diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index d6da4b818f..aa21a0edc8 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -749,7 +749,7 @@ InstructionQueue::scheduleReadyInsts() DynInstPtr deferred_mem_inst; int total_deferred_mem_issued = 0; while (total_deferred_mem_issued < totalWidth && - (deferred_mem_inst = getDeferredMemInstToExecute()) != NULL) { + (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { issueToExecuteQueue->access(0)->size++; instsToExecute.push_back(deferred_mem_inst); total_deferred_mem_issued++; diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index 8744a71225..4442cee412 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -287,20 +287,21 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Dcache_entry, L1_TBEs[in_msg.LineAddress]); - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 asks the L2 for it. trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, L1_TBEs[in_msg.LineAddress]); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Dcache_entry, L1_TBEs[in_msg.LineAddress]); + } + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, @@ -313,21 +314,23 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") } } } else { - // *** DATA ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Icache_entry, L1_TBEs[in_msg.LineAddress]); - } + // *** DATA ACCESS *** Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 ask the L2 for it trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, L1_TBEs[in_msg.LineAddress]); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Icache_entry, L1_TBEs[in_msg.LineAddress]); + } + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 4082f23c9f..7f0ab62a85 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -338,14 +338,6 @@ machine(L1Cache, "Directory protocol") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - // Check to see if it is in the OTHER L1 - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry, - TBEs[in_msg.LineAddress]); - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 asks the L2 for it. @@ -353,6 +345,14 @@ machine(L1Cache, "Directory protocol") in_msg.LineAddress, L1Icache_entry, TBEs[in_msg.LineAddress]); } else { + + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + // Check to see if it is in the OTHER L1 + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry, + TBEs[in_msg.LineAddress]); + } if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), @@ -369,14 +369,6 @@ machine(L1Cache, "Directory protocol") } else { // *** DATA ACCESS *** - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - // Check to see if it is in the OTHER L1 - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Icache_entry, TBEs[in_msg.LineAddress]); - } - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 ask the L2 for it @@ -384,6 +376,14 @@ machine(L1Cache, "Directory protocol") in_msg.LineAddress, L1Dcache_entry, TBEs[in_msg.LineAddress]); } else { + + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + // Check to see if it is in the OTHER L1 + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Icache_entry, TBEs[in_msg.LineAddress]); + } if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index 00e9404c9b..226f213744 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -647,20 +647,21 @@ machine(L1Cache, "Token protocol") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Dcache_entry, tbe); - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, tbe); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Dcache_entry, tbe); + } + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 trigger(mandatory_request_type_to_event(in_msg.Type), @@ -676,21 +677,21 @@ machine(L1Cache, "Token protocol") } else { // *** DATA ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Icache_entry, tbe); - } - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, tbe); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Icache_entry, tbe); + } + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 trigger(mandatory_request_type_to_event(in_msg.Type), diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 78bc9e3e73..ab2a6acf4c 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -377,26 +377,26 @@ machine(L1Cache, "AMD Hammer-like protocol") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { - trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); - } else { - trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(in_msg.LineAddress), - getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); - } - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, tbe); } else { + // Check to see if it is in the OTHER L1 + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { + trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); + } else { + trigger(Event:L2_Replacement, + L2cacheMemory.cacheProbe(in_msg.LineAddress), + getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), + TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); + } + } + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 @@ -430,26 +430,27 @@ machine(L1Cache, "AMD Hammer-like protocol") } else { // *** DATA ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { - trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); - } else { - trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(in_msg.LineAddress), - getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); - } - } - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, tbe); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { + trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); + } else { + trigger(Event:L2_Replacement, + L2cacheMemory.cacheProbe(in_msg.LineAddress), + getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), + TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); + } + } + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress); diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc index f6b79c5803..2255950053 100644 --- a/src/mem/ruby/buffers/MessageBuffer.cc +++ b/src/mem/ruby/buffers/MessageBuffer.cc @@ -58,6 +58,8 @@ MessageBuffer::MessageBuffer(const string &name) m_name = name; m_stall_msg_map.clear(); + m_input_link_id = 0; + m_vnet_id = 0; } int @@ -228,6 +230,7 @@ MessageBuffer::enqueue(MsgPtr message, Time delta) // Schedule the wakeup if (m_consumer_ptr != NULL) { g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, arrival_time); + m_consumer_ptr->storeEventInfo(m_vnet_id); } else { panic("No consumer: %s name: %s\n", *this, m_name); } diff --git a/src/mem/ruby/buffers/MessageBuffer.hh b/src/mem/ruby/buffers/MessageBuffer.hh index 62cc656701..88df5b788e 100644 --- a/src/mem/ruby/buffers/MessageBuffer.hh +++ b/src/mem/ruby/buffers/MessageBuffer.hh @@ -142,6 +142,9 @@ class MessageBuffer void printStats(std::ostream& out); void clearStats() { m_not_avail_count = 0; m_msg_counter = 0; } + void setIncomingLink(int link_id) { m_input_link_id = link_id; } + void setVnet(int net) { m_vnet_id = net; } + private: //added by SS int m_recycle_latency; @@ -184,6 +187,9 @@ class MessageBuffer bool m_ordering_set; bool m_randomization; Time m_last_arrival_time; + + int m_input_link_id; + int m_vnet_id; }; inline std::ostream& diff --git a/src/mem/ruby/common/Consumer.hh b/src/mem/ruby/common/Consumer.hh index c1f8bc42e6..a119abb390 100644 --- a/src/mem/ruby/common/Consumer.hh +++ b/src/mem/ruby/common/Consumer.hh @@ -67,6 +67,7 @@ class Consumer virtual void wakeup() = 0; virtual void print(std::ostream& out) const = 0; + virtual void storeEventInfo(int info) {} const Time& getLastScheduledWakeup() const diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc index 7229c724f0..5c461c63fe 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.cc +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc @@ -54,6 +54,11 @@ PerfectSwitch::PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr) m_round_robin_start = 0; m_network_ptr = network_ptr; m_wakeups_wo_switch = 0; + + for(int i = 0;i < m_virtual_networks;++i) + { + m_pending_message_count.push_back(0); + } } void @@ -62,12 +67,15 @@ PerfectSwitch::addInPort(const vector& in) assert(in.size() == m_virtual_networks); NodeID port = m_in.size(); m_in.push_back(in); + for (int j = 0; j < m_virtual_networks; j++) { m_in[port][j]->setConsumer(this); string desc = csprintf("[Queue from port %s %s %s to PerfectSwitch]", NodeIDToString(m_switch_id), NodeIDToString(port), NodeIDToString(j)); m_in[port][j]->setDescription(desc); + m_in[port][j]->setIncomingLink(port); + m_in[port][j]->setVnet(j); } } @@ -154,160 +162,169 @@ PerfectSwitch::wakeup() m_round_robin_start = 0; } - // for all input ports, use round robin scheduling - for (int counter = 0; counter < m_in.size(); counter++) { - // Round robin scheduling - incoming++; - if (incoming >= m_in.size()) { - incoming = 0; - } - - // temporary vectors to store the routing results - vector output_links; - vector output_link_destinations; - - // Is there a message waiting? - while (m_in[incoming][vnet]->isReady()) { - DPRINTF(RubyNetwork, "incoming: %d\n", incoming); - - // Peek at message - msg_ptr = m_in[incoming][vnet]->peekMsgPtr(); - net_msg_ptr = safe_cast(msg_ptr.get()); - DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr)); - - output_links.clear(); - output_link_destinations.clear(); - NetDest msg_dsts = - net_msg_ptr->getInternalDestination(); - - // Unfortunately, the token-protocol sends some - // zero-destination messages, so this assert isn't valid - // assert(msg_dsts.count() > 0); - - assert(m_link_order.size() == m_routing_table.size()); - assert(m_link_order.size() == m_out.size()); - - if (m_network_ptr->getAdaptiveRouting()) { - if (m_network_ptr->isVNetOrdered(vnet)) { - // Don't adaptively route - for (int out = 0; out < m_out.size(); out++) { - m_link_order[out].m_link = out; - m_link_order[out].m_value = 0; - } - } else { - // Find how clogged each link is - for (int out = 0; out < m_out.size(); out++) { - int out_queue_length = 0; - for (int v = 0; v < m_virtual_networks; v++) { - out_queue_length += m_out[out][v]->getSize(); - } - int value = - (out_queue_length << 8) | (random() & 0xff); - m_link_order[out].m_link = out; - m_link_order[out].m_value = value; - } - - // Look at the most empty link first - sort(m_link_order.begin(), m_link_order.end()); - } + if(m_pending_message_count[vnet] > 0) { + // for all input ports, use round robin scheduling + for (int counter = 0; counter < m_in.size(); counter++) { + // Round robin scheduling + incoming++; + if (incoming >= m_in.size()) { + incoming = 0; } - for (int i = 0; i < m_routing_table.size(); i++) { - // pick the next link to look at - int link = m_link_order[i].m_link; - NetDest dst = m_routing_table[link]; - DPRINTF(RubyNetwork, "dst: %s\n", dst); + // temporary vectors to store the routing results + vector output_links; + vector output_link_destinations; - if (!msg_dsts.intersectionIsNotEmpty(dst)) - continue; + // Is there a message waiting? + while (m_in[incoming][vnet]->isReady()) { + DPRINTF(RubyNetwork, "incoming: %d\n", incoming); - // Remember what link we're using - output_links.push_back(link); - - // Need to remember which destinations need this - // message in another vector. This Set is the - // intersection of the routing_table entry and the - // current destination set. The intersection must - // not be empty, since we are inside "if" - output_link_destinations.push_back(msg_dsts.AND(dst)); - - // Next, we update the msg_destination not to - // include those nodes that were already handled - // by this link - msg_dsts.removeNetDest(dst); - } - - assert(msg_dsts.count() == 0); - //assert(output_links.size() > 0); - - // Check for resources - for all outgoing queues - bool enough = true; - for (int i = 0; i < output_links.size(); i++) { - int outgoing = output_links[i]; - if (!m_out[outgoing][vnet]->areNSlotsAvailable(1)) - enough = false; - DPRINTF(RubyNetwork, "Checking if node is blocked\n" - "outgoing: %d, vnet: %d, enough: %d\n", - outgoing, vnet, enough); - } - - // There were not enough resources - if (!enough) { - g_eventQueue_ptr->scheduleEvent(this, 1); - DPRINTF(RubyNetwork, "Can't deliver message since a node " - "is blocked\n" - "Message: %s\n", (*net_msg_ptr)); - break; // go to next incoming port - } - - MsgPtr unmodified_msg_ptr; - - if (output_links.size() > 1) { - // If we are sending this message down more than - // one link (size>1), we need to make a copy of - // the message so each branch can have a different - // internal destination we need to create an - // unmodified MsgPtr because the MessageBuffer - // enqueue func will modify the message - - // This magic line creates a private copy of the - // message - unmodified_msg_ptr = msg_ptr->clone(); - } - - // Enqueue it - for all outgoing queues - for (int i=0; i 0) { - // create a private copy of the unmodified - // message - msg_ptr = unmodified_msg_ptr->clone(); - } - - // Change the internal destination set of the - // message so it knows which destinations this - // link is responsible for. + // Peek at message + msg_ptr = m_in[incoming][vnet]->peekMsgPtr(); net_msg_ptr = safe_cast(msg_ptr.get()); - net_msg_ptr->getInternalDestination() = - output_link_destinations[i]; + DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr)); - // Enqeue msg - DPRINTF(RubyNetwork, "Switch: %d enqueuing net msg from " - "inport[%d][%d] to outport [%d][%d] time: %lld.\n", - m_switch_id, incoming, vnet, outgoing, vnet, - g_eventQueue_ptr->getTime()); + output_links.clear(); + output_link_destinations.clear(); + NetDest msg_dsts = + net_msg_ptr->getInternalDestination(); - m_out[outgoing][vnet]->enqueue(msg_ptr); + // Unfortunately, the token-protocol sends some + // zero-destination messages, so this assert isn't valid + // assert(msg_dsts.count() > 0); + + assert(m_link_order.size() == m_routing_table.size()); + assert(m_link_order.size() == m_out.size()); + + if (m_network_ptr->getAdaptiveRouting()) { + if (m_network_ptr->isVNetOrdered(vnet)) { + // Don't adaptively route + for (int out = 0; out < m_out.size(); out++) { + m_link_order[out].m_link = out; + m_link_order[out].m_value = 0; + } + } else { + // Find how clogged each link is + for (int out = 0; out < m_out.size(); out++) { + int out_queue_length = 0; + for (int v = 0; v < m_virtual_networks; v++) { + out_queue_length += m_out[out][v]->getSize(); + } + int value = + (out_queue_length << 8) | (random() & 0xff); + m_link_order[out].m_link = out; + m_link_order[out].m_value = value; + } + + // Look at the most empty link first + sort(m_link_order.begin(), m_link_order.end()); + } + } + + for (int i = 0; i < m_routing_table.size(); i++) { + // pick the next link to look at + int link = m_link_order[i].m_link; + NetDest dst = m_routing_table[link]; + DPRINTF(RubyNetwork, "dst: %s\n", dst); + + if (!msg_dsts.intersectionIsNotEmpty(dst)) + continue; + + // Remember what link we're using + output_links.push_back(link); + + // Need to remember which destinations need this + // message in another vector. This Set is the + // intersection of the routing_table entry and the + // current destination set. The intersection must + // not be empty, since we are inside "if" + output_link_destinations.push_back(msg_dsts.AND(dst)); + + // Next, we update the msg_destination not to + // include those nodes that were already handled + // by this link + msg_dsts.removeNetDest(dst); + } + + assert(msg_dsts.count() == 0); + //assert(output_links.size() > 0); + + // Check for resources - for all outgoing queues + bool enough = true; + for (int i = 0; i < output_links.size(); i++) { + int outgoing = output_links[i]; + if (!m_out[outgoing][vnet]->areNSlotsAvailable(1)) + enough = false; + DPRINTF(RubyNetwork, "Checking if node is blocked\n" + "outgoing: %d, vnet: %d, enough: %d\n", + outgoing, vnet, enough); + } + + // There were not enough resources + if (!enough) { + g_eventQueue_ptr->scheduleEvent(this, 1); + DPRINTF(RubyNetwork, "Can't deliver message since a node " + "is blocked\n" + "Message: %s\n", (*net_msg_ptr)); + break; // go to next incoming port + } + + MsgPtr unmodified_msg_ptr; + + if (output_links.size() > 1) { + // If we are sending this message down more than + // one link (size>1), we need to make a copy of + // the message so each branch can have a different + // internal destination we need to create an + // unmodified MsgPtr because the MessageBuffer + // enqueue func will modify the message + + // This magic line creates a private copy of the + // message + unmodified_msg_ptr = msg_ptr->clone(); + } + + // Enqueue it - for all outgoing queues + for (int i=0; i 0) { + // create a private copy of the unmodified + // message + msg_ptr = unmodified_msg_ptr->clone(); + } + + // Change the internal destination set of the + // message so it knows which destinations this + // link is responsible for. + net_msg_ptr = safe_cast(msg_ptr.get()); + net_msg_ptr->getInternalDestination() = + output_link_destinations[i]; + + // Enqeue msg + DPRINTF(RubyNetwork, "Switch: %d enqueuing net msg from " + "inport[%d][%d] to outport [%d][%d] time: %lld.\n", + m_switch_id, incoming, vnet, outgoing, vnet, + g_eventQueue_ptr->getTime()); + + m_out[outgoing][vnet]->enqueue(msg_ptr); + } + + // Dequeue msg + m_in[incoming][vnet]->pop(); + m_pending_message_count[vnet]--; } - - // Dequeue msg - m_in[incoming][vnet]->pop(); } } } } +void +PerfectSwitch::storeEventInfo(int info) +{ + m_pending_message_count[info]++; +} + void PerfectSwitch::printStats(std::ostream& out) const { diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh index a7e577df01..cd0219fd9f 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.hh +++ b/src/mem/ruby/network/simple/PerfectSwitch.hh @@ -69,6 +69,7 @@ class PerfectSwitch : public Consumer int getOutLinks() const { return m_out.size(); } void wakeup(); + void storeEventInfo(int info); void printStats(std::ostream& out) const; void clearStats(); @@ -92,6 +93,7 @@ class PerfectSwitch : public Consumer int m_round_robin_start; int m_wakeups_wo_switch; SimpleNetwork* m_network_ptr; + std::vector m_pending_message_count; }; inline std::ostream& diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh index ff94fdd409..7fcfabe9ca 100644 --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -57,6 +57,8 @@ class Message : public RefCounted virtual Message* clone() const = 0; virtual void print(std::ostream& out) const = 0; + virtual void setIncomingLink(int) {} + virtual void setVnet(int) {} void setDelayedCycles(const int& cycles) { m_DelayedCycles = cycles; } const int& getDelayedCycles() const {return m_DelayedCycles;} diff --git a/src/mem/ruby/slicc_interface/NetworkMessage.hh b/src/mem/ruby/slicc_interface/NetworkMessage.hh index 082481e054..a8f9c625b3 100644 --- a/src/mem/ruby/slicc_interface/NetworkMessage.hh +++ b/src/mem/ruby/slicc_interface/NetworkMessage.hh @@ -82,9 +82,16 @@ class NetworkMessage : public Message virtual void print(std::ostream& out) const = 0; + int getIncomingLink() const { return incoming_link; } + void setIncomingLink(int link) { incoming_link = link; } + int getVnet() const { return vnet; } + void setVnet(int net) { vnet = net; } + private: NetDest m_internal_dest; bool m_internal_dest_valid; + int incoming_link; + int vnet; }; inline std::ostream& diff --git a/src/python/m5/main.py b/src/python/m5/main.py index cd139ccb39..23a012166a 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -61,8 +61,6 @@ add_option('-C', "--copyright", action="store_true", default=False, help="Show full copyright information") add_option('-R', "--readme", action="store_true", default=False, help="Show the readme") -add_option('-N', "--release-notes", action="store_true", default=False, - help="Show the release notes") # Options for configuring the base simulator add_option('-d', "--outdir", metavar="DIR", default="m5out", @@ -207,13 +205,6 @@ def main(): print info.README print - if options.release_notes: - done = True - print 'Release Notes:' - print - print info.RELEASE_NOTES - print - if options.trace_help: done = True check_tracing() diff --git a/system/alpha/console/Makefile b/system/alpha/console/Makefile new file mode 100644 index 0000000000..9fea133a2f --- /dev/null +++ b/system/alpha/console/Makefile @@ -0,0 +1,60 @@ +# Copyright (c) 2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan L. Binkert +# Ali G. Saidi + +# Point to the M5 diretory so we can get some headers +M5?=../../.. + +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), alpha) +CROSS_COMPILE?=alpha-unknown-linux-gnu- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld + +DBMENTRY= fffffc0000010000 +CFLAGS=-I . -I ../h -I$(M5)/src/dev/alpha -I$(M5)/util/m5/ -fno-builtin -Wa,-m21164 +OBJS=dbmentry.o printf.o paljtokern.o paljtoslave.o console.o m5op.o + +all: console + +m5op.o: $(M5)/util/m5/m5op_alpha.S + $(CC) $(CFLAGS) -nostdinc -o $@ -c $< + +%.o: %.S + $(CC) $(CFLAGS) -nostdinc -o $@ -c $< + +%.o: %.c + $(CC) -g3 $(CFLAGS) -o $@ -c $< + +console: $(OBJS) + $(LD) -o console -N -Ttext $(DBMENTRY) -non_shared $(OBJS) -lc + +clean: + rm -f *.o console diff --git a/system/alpha/console/console.c b/system/alpha/console/console.c new file mode 100644 index 0000000000..f57ce054f0 --- /dev/null +++ b/system/alpha/console/console.c @@ -0,0 +1,1074 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ****************************************** + * M5 Console + * ******************************************/ + +#include +#include + +#define CONSOLE +#include "access.h" +#include "cserve.h" +#include "rpb.h" + +#define CONS_INT_TX 0x01 /* interrupt enable / state bits */ +#define CONS_INT_RX 0x02 + +#define PAGE_SIZE (8192) + +#define KSTACK_REGION_VA 0x20040000 + +#define KSEG 0xfffffc0000000000 +#define K1BASE 0xfffffc8000000000 +#define KSEG_TO_PHYS(x) (((ulong)x) & ~KSEG) + +#define ROUNDUP8(x) ((ulong)(((ulong)x)+7) & ~7) +#define ROUNDUP128(x) ((ulong)(((ulong)x) + 127) & ~127) +#define ROUNDUP8K(x) ((ulong)(((ulong)(x)) + 8191) & ~8191) + +#define FIRST(x) ((((ulong)(x)) >> 33) & 0x3ff) +#define SECOND(x) ((((ulong)(x)) >> 23) & 0x3ff) +#define THIRD(x) ((((ulong)(x)) >> 13) & 0x3ff) +#define THIRD_XXX(x) ((((ulong)(x)) >> 13) & 0xfff) +#define PFN(x) ((((ulong)(x) & ~KSEG) >> 13)) + +/* Kernel write | kernel read | valid */ +#define KPTE(x) ((ulong)((((ulong)(x)) << 32) | 0x1101)) + +#define HWRPB_PAGES 16 + +#define NUM_KERNEL_THIRD (4) + +#define printf_lock(args...) \ + do { \ + SpinLock(&theLock); \ + printf(args); \ + SpinUnlock(&theLock); \ + } while (0) + + +void unixBoot(int argc, char **argv); +void JToKern(char *bootadr, ulong rpb_percpu, ulong free_pfn, ulong k_argc, + char **k_argv, char **envp); +void JToPal(ulong bootadr); +void SlaveLoop(int cpu); + +volatile struct AlphaAccess *m5AlphaAccess; +struct AlphaAccess m5Conf; + +ulong theLock; + +extern void SpinLock(ulong *lock); +#define SpinUnlock(_x) *(_x) = 0; + +struct _kernel_params { + char *bootadr; + ulong rpb_percpu; + ulong free_pfn; + ulong argc; + ulong argv; + ulong envp; /* NULL */ +}; + +extern consoleCallback[]; +extern consoleFixup[]; +long CallBackDispatcher(); +long CallBackFixup(); + +/* + * m5 console output + */ + +void +InitConsole() +{ +} + +char +GetChar() +{ + return m5AlphaAccess->inputChar; +} + +void +PutChar(char c) +{ + m5AlphaAccess->outputChar = c; +} + +int +passArgs(int argc) +{ + return 0; +} + +int +main(int argc, char **argv) +{ + int x, i; + uint *k1ptr, *ksegptr; + + InitConsole(); + printf_lock("M5 console: m5AlphaAccess @ 0x%x\n", m5AlphaAccess); + + /* + * get configuration from backdoor + */ + m5Conf.last_offset = m5AlphaAccess->last_offset; + printf_lock("Got Configuration %d\n", m5Conf.last_offset); + + m5Conf.last_offset = m5AlphaAccess->last_offset; + m5Conf.version = m5AlphaAccess->version; + m5Conf.numCPUs = m5AlphaAccess->numCPUs; + m5Conf.intrClockFrequency = m5AlphaAccess->intrClockFrequency; + m5Conf.cpuClock = m5AlphaAccess->cpuClock; + m5Conf.mem_size = m5AlphaAccess->mem_size; + m5Conf.kernStart = m5AlphaAccess->kernStart; + m5Conf.kernEnd = m5AlphaAccess->kernEnd; + m5Conf.entryPoint = m5AlphaAccess->entryPoint; + m5Conf.diskUnit = m5AlphaAccess->diskUnit; + m5Conf.diskCount = m5AlphaAccess->diskCount; + m5Conf.diskPAddr = m5AlphaAccess->diskPAddr; + m5Conf.diskBlock = m5AlphaAccess->diskBlock; + m5Conf.diskOperation = m5AlphaAccess->diskOperation; + m5Conf.outputChar = m5AlphaAccess->outputChar; + m5Conf.inputChar = m5AlphaAccess->inputChar; + + if (m5Conf.version != ALPHA_ACCESS_VERSION) { + panic("Console version mismatch. Console expects %d. has %d \n", + ALPHA_ACCESS_VERSION, m5Conf.version); + } + + /* + * setup arguments to kernel + */ + unixBoot(argc, argv); + + panic("unix failed to boot\n"); + return 1; +} + +/* + * BOOTING + */ +struct rpb m5_rpb = { + NULL, /* 000: physical self-reference */ + ((long)'H') | (((long)'W') << 8) | (((long)'R') << 16) | + ((long)'P' << 24) | (((long)'B') << 32), /* 008: contains "HWRPB" */ + 6, /* 010: HWRPB version number */ + /* the byte count is wrong, but who needs it? - lance */ + 0, /* 018: bytes in RPB perCPU CTB CRB MEDSC */ + 0, /* 020: primary cpu id */ + PAGE_SIZE, /* 028: page size in bytes */ + 43, /* 030: number of phys addr bits */ + 127, /* 038: max valid ASN */ + {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1'}, + /* 040: system serial num: 10 ascii chars */ + 0, /* OVERRIDDEN */ + (1<<10), /* 058: system variation */ + 'c'|('o'<<8)|('o'<<16)|('l'<< 24), /* 060: system revision */ + 1024*4096, /* 068: scaled interval clock intr freq */ + 0, /* 070: cycle counter frequency */ + 0x200000000, /* 078: virtual page table base */ + 0, /* 080: reserved */ + 0, /* 088: offset to translation buffer hint */ + 1, /* 090: number of processor slots OVERRIDDEN*/ + sizeof(struct rpb_percpu), /* 098: per-cpu slot size. OVERRIDDEN */ + 0, /* 0A0: offset to per_cpu slots */ + 1, /* 0A8: number of CTBs */ + sizeof(struct ctb_tt), + 0, /* 0B8: offset to CTB (cons term block) */ + 0, /* 0C0: offset to CRB (cons routine block) */ + 0, /* 0C8: offset to memory descriptor table */ + 0, /* 0D0: offset to config data block */ + 0, /* 0D8: offset to FRU table */ + 0, /* 0E0: virt addr of save term routine */ + 0, /* 0E8: proc value for save term routine */ + 0, /* 0F0: virt addr of restore term routine */ + 0, /* 0F8: proc value for restore term routine */ + 0, /* 100: virt addr of CPU restart routine */ + 0, /* 108: proc value for CPU restart routine */ + 0, /* 110: used to determine presence of kdebug */ + 0, /* 118: reserved for hardware */ +/* the checksum is wrong, but who needs it? - lance */ + 0, /* 120: checksum of prior entries in rpb */ + 0, /* 128: receive ready bitmask */ + 0, /* 130: transmit ready bitmask */ + 0, /* 138: Dynamic System Recog. offset */ +}; + +ulong m5_tbb[] = { 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, + 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, + 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, + 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e }; + +struct rpb_percpu m5_rpb_percpu = { + {0,0,0,0,0,0,1,{0,0},{0,0,0,0,0,0,0,0}}, /* 000: boot/restart HWPCB */ + (STATE_PA | STATE_PP | STATE_CV | + STATE_PV | STATE_PMV | STATE_PL), /* 080: per-cpu state bits */ + 0xc000, /* 088: palcode memory length */ + 0x2000, /* 090: palcode scratch length */ + 0x4000, /* 098: paddr of pal mem space */ + 0x2000, /* 0A0: paddr of pal scratch space */ + (2 << 16) | (5 << 8) | 1, /* 0A8: PALcode rev required */ + 11 | (2L << 32), /* 0B0: processor type */ + 7, /* 0B8: processor variation */ + 'M'|('5'<<8)|('A'<<16)|('0'<<24), /* 0C0: processor revision */ + {'M','5','/','A','l','p','h','a','0','0','0','0','0','0','0','0'}, + /* 0C8: proc serial num: 10 chars */ + 0, /* 0D8: phys addr of logout area */ + 0, /* 0E0: len in bytes of logout area */ + 0, /* 0E8: halt pcb base */ + 0, /* 0F0: halt pc */ + 0, /* 0F8: halt ps */ + 0, /* 100: halt arg list (R25) */ + 0, /* 108: halt return address (R26) */ + 0, /* 110: halt procedure value (R27) */ + 0, /* 118: reason for halt */ + 0, /* 120: for software */ + {0}, /* 128: inter-console comm buffer */ + {1,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0}, /* 1D0: PALcode revs available */ + 0 /* 250: reserved for arch use */ +/* the dump stack grows from the end of the rpb page not to reach here */ +}; + +struct _m5_rpb_mdt { + long rpb_checksum; /* 000: checksum of entire mem desc table */ + long rpb_impaddr; /* 008: PA of implementation dep info */ + long rpb_numcl; /* 010: number of clusters */ + struct rpb_cluster rpb_cluster[3]; /* first instance of a cluster */ +}; + +struct _m5_rpb_mdt m5_rpb_mdt = { + 0, /* 000: checksum of entire mem desc table */ + 0, /* 008: PA of implementation dep info */ + 0, /* 010: number of clusters */ + {{ 0, /* 000: starting PFN of this cluster */ + 0, /* 008: count of PFNs in this cluster */ + 0, /* 010: count of tested PFNs in cluster */ + 0, /* 018: va of bitmap */ + 0, /* 020: pa of bitmap */ + 0, /* 028: checksum of bitmap */ + 1 /* 030: usage of cluster */ + }, + { 0, /* 000: starting PFN of this cluster */ + 0, /* 008: count of PFNs in this cluster */ + 0, /* 010: count of tested PFNs in cluster */ + 0, /* 018: va of bitmap */ + 0, /* 020: pa of bitmap */ + 0, /* 028: checksum of bitmap */ + 0 /* 030: usage of cluster */ + }, + { 0, /* 000: starting PFN of this cluster */ + 0, /* 008: count of PFNs in this cluster */ + 0, /* 010: count of tested PFNs in cluster */ + 0, /* 018: va of bitmap */ + 0, /* 020: pa of bitmap */ + 0, /* 028: checksum of bitmap */ + 0 /* 030: usage of cluster */ + }} +}; + +/* constants for slotinfo bus_type subfield */ +#define SLOTINFO_TC 0 +#define SLOTINFO_ISA 1 +#define SLOTINFO_EISA 2 +#define SLOTINFO_PCI 3 + +struct rpb_ctb m5_rpb_ctb = { + CONS_DZ, /* 000: console type */ + 0, /* 008: console unit */ + 0, /* 010: reserved */ + 0 /* 018: byte length of device dep portion */ +}; + +/* we don't do any fixup (aka relocate the console) - we hope */ +struct rpb_crb m5_rpb_crb = { + 0, /* va of call-back dispatch rtn */ + 0, /* pa of call-back dispatch rtn */ + 0, /* va of call-back fixup rtn */ + 0, /* pa of call-back fixup rtn */ + 0, /* number of entries in phys/virt map */ + 0 /* Number of pages to be mapped */ +}; + +struct _rpb_name { + ulong length; + char name[16]; +}; + +extern struct _rpb_name m5_name; + +struct rpb_dsr m5_rpb_dsr = { + 0, + 0, + 0, +}; + +struct _rpb_name m5_name = { + 16, + {'U','M','I','C','H',' ','M','5','/','A','L','P','H','A',' ',0}, +}; + +/* + * M5 has one LURT entry: + * 1050 is for workstations + * 1100 is servers (and is needed for CXX) + */ +long m5_lurt[10] = { 9, 12, -1, -1, -1, -1, -1, -1, 1100, 1100 }; + +ulong unix_boot_mem; +ulong bootadr; + +char **kargv; +int kargc; +ulong free_pfn; +struct rpb_percpu *rpb_percpu; + +char * +unix_boot_alloc(int pages) +{ + char *ret = (char *)unix_boot_mem; + unix_boot_mem += (pages * PAGE_SIZE); + return ret; +} + +ulong *first = 0; +ulong *third_rpb = 0; +ulong *reservedFixup = 0; + +int strcpy(char *dst, char *src); + +struct rpb *rpb; +extern ulong _end; + +void +unixBoot(int argc, char **argv) +{ + ulong *second, *third_kernel, ptr, *tbb, size, *percpu_logout; + unsigned char *mdt_bitmap; + long *lp1, *lp2, sum; + int i, cl; + ulong kern_first_page; + ulong mem_size = m5Conf.mem_size; + + ulong mem_pages = mem_size / PAGE_SIZE, cons_pages; + ulong mdt_bitmap_pages = mem_pages / (PAGE_SIZE*8); + + ulong kernel_bytes, ksp, kernel_end, *unix_kernel_stack, bss, + ksp_bottom, ksp_top; + struct rpb_ctb *rpb_ctb; + struct ctb_tt *ctb_tt; + struct rpb_dsr *rpb_dsr; + struct rpb_crb *rpb_crb; + struct _m5_rpb_mdt *rpb_mdt; + int *rpb_lurt; + char *rpb_name; + ulong nextPtr; + + printf_lock("memsize %x pages %x \n", mem_size, mem_pages); + + /* Allocate: + * two pages for the HWRPB + * five page table pages: + * 1: First level page table + * 1: Second level page table + * 1: Third level page table for HWRPB + * 2: Third level page table for kernel (for up to 16MB) + * set up the page tables + * load the kernel at the physical address 0x230000 + * build the HWRPB + * set up memory descriptor table to give up the + * physical memory between the end of the page + * tables and the start of the kernel + * enable kseg addressing + * jump to the kernel + */ + + unix_boot_mem = ROUNDUP8K(&_end); + + printf_lock("First free page after ROM 0x%x\n", unix_boot_mem); + + rpb = (struct rpb *)unix_boot_alloc(HWRPB_PAGES); + + mdt_bitmap = (unsigned char *)unix_boot_alloc(mdt_bitmap_pages); + first = (ulong *)unix_boot_alloc(1); + second = (ulong *)unix_boot_alloc(1); + third_rpb = (ulong *)unix_boot_alloc(1); + reservedFixup = (ulong*) unix_boot_alloc(1); + third_kernel = (ulong *)unix_boot_alloc(NUM_KERNEL_THIRD); + percpu_logout = (ulong*)unix_boot_alloc(1); + + cons_pages = KSEG_TO_PHYS(unix_boot_mem) / PAGE_SIZE; + + /* Set up the page tables */ + bzero((char *)first, PAGE_SIZE); + bzero((char *)second, PAGE_SIZE); + bzero((char *)reservedFixup, PAGE_SIZE); + bzero((char *)third_rpb, HWRPB_PAGES * PAGE_SIZE); + bzero((char *)third_kernel, PAGE_SIZE * NUM_KERNEL_THIRD); + + first[0] = KPTE(PFN(second)); + first[1] = KPTE(PFN(first)); /* Region 3 */ + + /* Region 0 */ + second[SECOND(0x10000000)] = KPTE(PFN(third_rpb)); + + for (i = 0; i < NUM_KERNEL_THIRD; i++) { + /* Region 1 */ + second[SECOND(0x20000000) + i] = KPTE(PFN(third_kernel) + i); + } + + /* Region 2 */ + second[SECOND(0x40000000)] = KPTE(PFN(second)); + + + /* For some obscure reason, Dec Unix's database read + * from /etc/sysconfigtab is written to this fixed + * mapped memory location. Go figure, since it is + * not initialized by the console. Maybe it is + * to look at the database from the console + * after a boot/crash. + * + * Black magic to estimate the max size. SEGVs on overflow + * bugnion + */ + +#define DATABASE_BASE 0x20000000 +#define DATABASE_END 0x20020000 + + ulong *dbPage = (ulong*)unix_boot_alloc(1); + bzero(dbPage, PAGE_SIZE); + second[SECOND(DATABASE_BASE)] = KPTE(PFN(dbPage)); + for (i = DATABASE_BASE; i < DATABASE_END ; i += PAGE_SIZE) { + ulong *db = (ulong*)unix_boot_alloc(1); + dbPage[THIRD(i)] = KPTE(PFN(db)); + } + + /* Region 0 */ + /* Map the HWRPB */ + for (i = 0; i < HWRPB_PAGES; i++) + third_rpb[i] = KPTE(PFN(rpb) + i); + + /* Map the MDT bitmap table */ + for (i = 0; i < mdt_bitmap_pages; i++) { + third_rpb[HWRPB_PAGES + i] = KPTE(PFN(mdt_bitmap) + i); + } + + /* Protect the PAL pages */ + for (i = 1; i < PFN(first); i++) + third_rpb[HWRPB_PAGES + mdt_bitmap_pages + i] = KPTE(i); + + /* Set up third_kernel after it's loaded, when we know where it is */ + kern_first_page = (KSEG_TO_PHYS(m5Conf.kernStart)/PAGE_SIZE); + kernel_end = ROUNDUP8K(m5Conf.kernEnd); + bootadr = m5Conf.entryPoint; + + printf_lock("HWRPB 0x%x l1pt 0x%x l2pt 0x%x l3pt_rpb 0x%x l3pt_kernel 0x%x" + " l2reserv 0x%x\n", + rpb, first, second, third_rpb, third_kernel, reservedFixup); + if (kernel_end - m5Conf.kernStart > (0x800000*NUM_KERNEL_THIRD)) { + printf_lock("Kernel is more than 8MB 0x%x - 0x%x = 0x%x\n", + kernel_end, m5Conf.kernStart, + kernel_end - m5Conf.kernStart ); + panic("kernel too big\n"); + } + printf_lock("kstart = 0x%x, kend = 0x%x, kentry = 0x%x, numCPUs = 0x%x\n", m5Conf.kernStart, m5Conf.kernEnd, m5Conf.entryPoint, m5Conf.numCPUs); + ksp_bottom = (ulong)unix_boot_alloc(1); + ksp_top = ksp_bottom + PAGE_SIZE; + ptr = (ulong) ksp_bottom; + bzero((char *)ptr, PAGE_SIZE); + dbPage[THIRD(KSTACK_REGION_VA)] = 0; /* Stack Guard Page */ + dbPage[THIRD(KSTACK_REGION_VA + PAGE_SIZE)] = KPTE(PFN(ptr)); /* Kernel Stack Page */ + dbPage[THIRD(KSTACK_REGION_VA + 2*PAGE_SIZE)] = 0; /* Stack Guard Page */ + + /* put argv into the bottom of the stack - argv starts at 1 because + * the command thatr got us here (i.e. "unixboot) is in argv[0]. + */ + ksp = ksp_top - 8; /* Back up one longword */ + ksp -= argc * sizeof(char *); /* Make room for argv */ + kargv = (char **) ksp; + for (i = 1; i < argc; i++) { /* Copy arguments to stack */ + ksp -= ((strlen(argv[i]) + 1) + 7) & ~0x7; + kargv[i-1] = (char *) ksp; + strcpy(kargv[i - 1], argv[i]); + } + kargc = i - 1; + kargv[kargc] = NULL; /* just to be sure; doesn't seem to be used */ + ksp -= sizeof(char *); /* point above last arg for no real reason */ + + free_pfn = PFN(kernel_end); + + bcopy((char *)&m5_rpb, (char *)rpb, sizeof(struct rpb)); + + rpb->rpb_selfref = (struct rpb *) KSEG_TO_PHYS(rpb); + rpb->rpb_string = 0x0000004250525748; + + tbb = (ulong *) (((char *) rpb) + ROUNDUP8(sizeof(struct rpb))); + rpb->rpb_trans_off = (ulong)tbb - (ulong)rpb; + bcopy((char *)m5_tbb, (char *)tbb, sizeof(m5_tbb)); + + /* + * rpb_counter. Use to determine timeouts in OS. + * XXX must be patched after a checkpoint restore (I guess) + */ + + printf_lock("CPU Clock at %d MHz IntrClockFrequency=%d \n", + m5Conf.cpuClock, m5Conf.intrClockFrequency); + rpb->rpb_counter = m5Conf.cpuClock * 1000 * 1000; + + /* + * By definition, the rpb_clock is scaled by 4096 (in hz) + */ + rpb->rpb_clock = m5Conf.intrClockFrequency * 4096; + + /* + * Per CPU Slots. Multiprocessor support. + */ + int percpu_size = ROUNDUP128(sizeof(struct rpb_percpu)); + + printf_lock("Booting with %d processor(s) \n", m5Conf.numCPUs); + + rpb->rpb_numprocs = m5Conf.numCPUs; + rpb->rpb_slotsize = percpu_size; + rpb_percpu = (struct rpb_percpu *) + ROUNDUP128(((ulong)tbb) + (sizeof(m5_tbb))); + + rpb->rpb_percpu_off = (ulong)rpb_percpu - (ulong)rpb; + + for (i = 0; i < m5Conf.numCPUs; i++) { + struct rpb_percpu *thisCPU = (struct rpb_percpu*) + ((ulong)rpb_percpu + percpu_size * i); + + bzero((char *)thisCPU, percpu_size); + bcopy((char *)&m5_rpb_percpu, (char *)thisCPU, + sizeof(struct rpb_percpu)); + + thisCPU->rpb_pcb.rpb_ksp = (KSTACK_REGION_VA + 2*PAGE_SIZE - (ksp_top - ksp)); + thisCPU->rpb_pcb.rpb_ptbr = PFN(first); + + thisCPU->rpb_logout = KSEG_TO_PHYS(percpu_logout); + thisCPU->rpb_logout_len = PAGE_SIZE; + + printf_lock("KSP: 0x%x PTBR 0x%x\n", + thisCPU->rpb_pcb.rpb_ksp, thisCPU->rpb_pcb.rpb_ptbr); + } + + nextPtr = (ulong)rpb_percpu + percpu_size * m5Conf.numCPUs; + + /* + * Console Terminal Block + */ + rpb_ctb = (struct rpb_ctb *) nextPtr; + ctb_tt = (struct ctb_tt*) rpb_ctb; + + rpb->rpb_ctb_off = ((ulong)rpb_ctb) - (ulong)rpb; + rpb->rpb_ctb_size = sizeof(struct rpb_ctb); + + bzero((char *)rpb_ctb, sizeof(struct ctb_tt)); + + rpb_ctb->rpb_type = CONS_DZ; + rpb_ctb->rpb_length = sizeof(ctb_tt) - sizeof(rpb_ctb); + + /* + * uart initizliation + */ + ctb_tt->ctb_tintr_vec = 0x6c0; /* matches tlaser pal code */ + ctb_tt->ctb_rintr_vec = 0x680; /* matches tlaser pal code */ + ctb_tt->ctb_term_type = CTB_GRAPHICS; + + rpb_crb = (struct rpb_crb *) (((ulong)rpb_ctb) + sizeof(struct ctb_tt)); + rpb->rpb_crb_off = ((ulong)rpb_crb) - (ulong)rpb; + + bzero((char *)rpb_crb, sizeof(struct rpb_crb)); + + /* + * console callback stuff (m5) + */ + rpb_crb->rpb_num = 1; + rpb_crb->rpb_mapped_pages = HWRPB_PAGES; + rpb_crb->rpb_map[0].rpb_virt = 0x10000000; + rpb_crb->rpb_map[0].rpb_phys = KSEG_TO_PHYS(((ulong)rpb) & ~0x1fff); + rpb_crb->rpb_map[0].rpb_pgcount = HWRPB_PAGES; + + printf_lock("Console Callback at 0x%x, fixup at 0x%x, crb offset: 0x%x\n", + rpb_crb->rpb_va_disp, rpb_crb->rpb_va_fixup, rpb->rpb_crb_off); + + rpb_mdt = (struct _m5_rpb_mdt *)((ulong)rpb_crb + sizeof(struct rpb_crb)); + rpb->rpb_mdt_off = (ulong)rpb_mdt - (ulong)rpb; + bcopy((char *)&m5_rpb_mdt, (char *)rpb_mdt, sizeof(struct _m5_rpb_mdt)); + + + cl = 0; + rpb_mdt->rpb_cluster[cl].rpb_pfncount = kern_first_page; + cl++; + + rpb_mdt->rpb_cluster[cl].rpb_pfn = kern_first_page; + rpb_mdt->rpb_cluster[cl].rpb_pfncount = mem_pages - kern_first_page; + rpb_mdt->rpb_cluster[cl].rpb_pfntested = + rpb_mdt->rpb_cluster[cl].rpb_pfncount; + rpb_mdt->rpb_cluster[cl].rpb_pa = KSEG_TO_PHYS(mdt_bitmap); + rpb_mdt->rpb_cluster[cl].rpb_va = 0x10000000 + HWRPB_PAGES * PAGE_SIZE; + cl++; + + rpb_mdt->rpb_numcl = cl; + + for (i = 0; i < cl; i++) + printf_lock("Memory cluster %d [%d - %d]\n", i, + rpb_mdt->rpb_cluster[i].rpb_pfn, + rpb_mdt->rpb_cluster[i].rpb_pfncount); + + /* Checksum the rpb for good luck */ + sum = 0; + lp1 = (long *)&rpb_mdt->rpb_impaddr; + lp2 = (long *)&rpb_mdt->rpb_cluster[cl]; + while (lp1 < lp2) sum += *lp1++; + rpb_mdt->rpb_checksum = sum; + + /* XXX should checksum the cluster descriptors */ + bzero((char *)mdt_bitmap, mdt_bitmap_pages * PAGE_SIZE); + for (i = 0; i < mem_pages/8; i++) + ((unsigned char *)mdt_bitmap)[i] = 0xff; + + printf_lock("Initalizing mdt_bitmap addr 0x%x mem_pages %x \n", + (long)mdt_bitmap,(long)mem_pages); + + m5_rpb.rpb_config_off = 0; + m5_rpb.rpb_fru_off = 0; + + rpb_dsr = (struct rpb_dsr *)((ulong)rpb_mdt + sizeof(struct _m5_rpb_mdt)); + rpb->rpb_dsr_off = (ulong)rpb_dsr - (ulong)rpb; + bzero((char *)rpb_dsr, sizeof(struct rpb_dsr)); + rpb_dsr->rpb_smm = 1578; /* Official XXM SMM number as per SRM */ + rpb_dsr->rpb_smm = 1089; /* Official Alcor SMM number as per SRM */ + + rpb_lurt = (int *) ROUNDUP8((ulong)rpb_dsr + sizeof(struct rpb_dsr)); + rpb_dsr->rpb_lurt_off = ((ulong) rpb_lurt) - (ulong) rpb_dsr; + bcopy((char *)m5_lurt, (char *)rpb_lurt, sizeof(m5_lurt)); + + rpb_name = (char *) ROUNDUP8(((ulong)rpb_lurt) + sizeof(m5_lurt)); + rpb_dsr->rpb_sysname_off = ((ulong) rpb_name) - (ulong) rpb_dsr; +#define THENAME " M5/Alpha " + sum = sizeof(THENAME); + bcopy(THENAME, rpb_name, sum); + *(ulong *)rpb_name = sizeof(THENAME); /* put in length field */ + + /* calculate size of rpb */ + rpb->rpb_size = ((ulong) &rpb_name[sum]) - (ulong)rpb; + + if (rpb->rpb_size > PAGE_SIZE * HWRPB_PAGES) { + panic("HWRPB_PAGES=%d too small for HWRPB !!! \n"); + } + + ulong *rpbptr = (ulong*)((char*)rpb_dsr + sizeof(struct rpb_dsr)); + rpb_crb->rpb_pa_disp = KSEG_TO_PHYS(rpbptr); + rpb_crb->rpb_va_disp = 0x10000000 + + (((ulong)rpbptr - (ulong)rpb) & (0x2000 * HWRPB_PAGES - 1)); + printf_lock("ConsoleDispatch at virt %x phys %x val %x\n", + rpb_crb->rpb_va_disp, rpb_crb->rpb_pa_disp, consoleCallback); + *rpbptr++ = 0; + *rpbptr++ = (ulong) consoleCallback; + rpb_crb->rpb_pa_fixup = KSEG_TO_PHYS(rpbptr); + rpb_crb->rpb_va_fixup = 0x10000000 + + (((ulong)rpbptr - (ulong)rpb) & (0x2000 * HWRPB_PAGES - 1)); + *rpbptr++ = 0; + + *rpbptr++ = (ulong) consoleFixup; + + /* Checksum the rpb for good luck */ + sum = 0; + lp1 = (long *)rpb; + lp2 = &rpb->rpb_checksum; + while (lp1 < lp2) + sum += *lp1++; + *lp2 = sum; + + /* + * MP bootstrap + */ + for (i = 1; i < m5Conf.numCPUs; i++) { + ulong stack = (ulong)unix_boot_alloc(1); + printf_lock("Bootstraping CPU %d with sp=0x%x\n", i, stack); + m5AlphaAccess->cpuStack[i] = stack; + } + + /* + * Make sure that we are not stepping on the kernel + */ + if ((ulong)unix_boot_mem >= (ulong)m5Conf.kernStart) { + panic("CONSOLE: too much memory. Smashing kernel\n"); + } else { + printf_lock("unix_boot_mem ends at %x \n", unix_boot_mem); + } + + JToKern((char *)bootadr, (ulong)rpb_percpu, free_pfn, kargc, kargv, NULL); +} + + +void +JToKern(char *bootadr, ulong rpb_percpu, ulong free_pfn, ulong k_argc, + char **k_argv, char **envp) +{ + extern ulong palJToKern[]; + + struct _kernel_params *kernel_params = (struct _kernel_params *) KSEG; + int i; + + printf_lock("k_argc = %d ", k_argc); + for (i = 0; i < k_argc; i++) { + printf_lock("'%s' ", k_argv[i]); + } + printf_lock("\n"); + + kernel_params->bootadr = bootadr; + kernel_params->rpb_percpu = KSEG_TO_PHYS(rpb_percpu); + kernel_params->free_pfn = free_pfn; + kernel_params->argc = k_argc; + kernel_params->argv = (ulong)k_argv; + kernel_params->envp = (ulong)envp; + printf_lock("jumping to kernel at 0x%x, (PCBB 0x%x pfn %d)\n", + bootadr, rpb_percpu, free_pfn); + JToPal(KSEG_TO_PHYS(palJToKern)); + printf_lock("returned from JToPal. Looping\n"); + while (1) + continue; +} + +void +JToPal(ulong bootadr) +{ + cServe(bootadr, 0, CSERVE_K_JTOPAL); + + /* + * Make sure that floating point is enabled incase + * it was disabled by the user program. + */ + wrfen(1); +} + +int +strcpy(char *dst, char *src) +{ + int i = 0; + while (*src) { + *dst++ = *src++; + i++; + } + return i; +} + +/* + * Console I/O + * + */ + +int numOpenDevices = 11; +struct { + char name[128]; +} deviceState[32]; + +#define BOOTDEVICE_NAME "SCSI 1 0 0 1 100 0" + +void +DeviceOperation(long op, long channel, long count, long address, long block) +{ + long pAddr; + + if (strcmp(deviceState[channel].name, BOOTDEVICE_NAME )) { + panic("DeviceRead: only implemented for root disk \n"); + } + pAddr = KSEG_TO_PHYS(address); + if (pAddr + count > m5Conf.mem_size) { + panic("DeviceRead: request out of range \n"); + } + + m5AlphaAccess->diskCount = count; + m5AlphaAccess->diskPAddr = pAddr; + m5AlphaAccess->diskBlock = block; + m5AlphaAccess->diskOperation = op; /* launch */ +} + +/* + * M5 Console callbacks + * + */ + +/* AXP manual 2-31 */ +#define CONSCB_GETC 0x1 +#define CONSCB_PUTS 0x2 +#define CONSCB_RESET_TERM 0x3 +#define CONSCB_SET_TERM_INT 0x4 +#define CONSCB_SET_TERM_CTL 0x5 +#define CONSCB_PROCESS_KEY 0x6 +#define CONSCB_OPEN_CONSOLE 0x7 +#define CONSCB_CLOSE_CONSOLE 0x8 + +#define CONSCB_OPEN 0x10 +#define CONSCB_CLOSE 0x11 +#define CONSCB_READ 0x13 + +#define CONSCB_GETENV 0x22 + +/* AXP manual 2-26 */ +#define ENV_AUTO_ACTION 0X01 +#define ENV_BOOT_DEV 0X02 +#define ENV_BOOTDEF_DEV 0X03 +#define ENV_BOOTED_DEV 0X04 +#define ENV_BOOT_FILE 0X05 +#define ENV_BOOTED_FILE 0X06 +#define ENV_BOOT_OSFLAGS 0X07 +#define ENV_BOOTED_OSFLAGS 0X08 +#define ENV_BOOT_RESET 0X09 +#define ENV_DUMP_DEV 0X0A +#define ENV_ENABLE_AUDIT 0X0B +#define ENV_LICENSE 0X0C +#define ENV_CHAR_SET 0X0D +#define ENV_LANGUAGE 0X0E +#define ENV_TTY_DEV 0X0F +#define ENV_SCSIID 0X42 +#define ENV_SCSIFAST 0X43 +#define ENV_COM1_BAUD 0X44 +#define ENV_COM1_MODEM 0X45 +#define ENV_COM1_FLOW 0X46 +#define ENV_COM1_MISC 0X47 +#define ENV_COM2_BAUD 0X48 +#define ENV_COM2_MODEM 0X49 +#define ENV_COM2_FLOW 0X4A +#define ENV_COM2_MISC 0X4B +#define ENV_PASSWORD 0X4C +#define ENV_SECURE 0X4D +#define ENV_LOGFAIL 0X4E +#define ENV_SRM2DEV_ID 0X4F + +#define MAX_ENVLEN 32 + +char env_auto_action[MAX_ENVLEN] = "BOOT"; +char env_boot_dev[MAX_ENVLEN] = ""; +char env_bootdef_dev[MAX_ENVLEN] = ""; +char env_booted_dev[MAX_ENVLEN] = BOOTDEVICE_NAME; +char env_boot_file[MAX_ENVLEN] = ""; +char env_booted_file[MAX_ENVLEN] = ""; +char env_boot_osflags[MAX_ENVLEN] = ""; +char env_booted_osflags[MAX_ENVLEN] = ""; +char env_boot_reset[MAX_ENVLEN] = ""; +char env_dump_dev[MAX_ENVLEN] = ""; +char env_enable_audit[MAX_ENVLEN] = ""; +char env_license[MAX_ENVLEN] = ""; +char env_char_set[MAX_ENVLEN] = ""; +char env_language[MAX_ENVLEN] = ""; +char env_tty_dev[MAX_ENVLEN] = "0"; +char env_scsiid[MAX_ENVLEN] = ""; +char env_scsifast[MAX_ENVLEN] = ""; +char env_com1_baud[MAX_ENVLEN] = ""; +char env_com1_modem[MAX_ENVLEN] = ""; +char env_com1_flow[MAX_ENVLEN] = ""; +char env_com1_misc[MAX_ENVLEN] = ""; +char env_com2_baud[MAX_ENVLEN] = ""; +char env_com2_modem[MAX_ENVLEN] = ""; +char env_com2_flow[MAX_ENVLEN] = ""; +char env_com2_misc[MAX_ENVLEN] = ""; +char env_password[MAX_ENVLEN] = ""; +char env_secure[MAX_ENVLEN] = ""; +char env_logfail[MAX_ENVLEN] = ""; +char env_srm2dev_id[MAX_ENVLEN] = ""; + +#define MAX_ENV_INDEX 100 +char *envptr[MAX_ENV_INDEX] = { + 0, /* 0x00 */ + env_auto_action, /* 0x01 */ + env_boot_dev, /* 0x02 */ + env_bootdef_dev, /* 0x03 */ + env_booted_dev, /* 0x04 */ + env_boot_file, /* 0x05 */ + env_booted_file, /* 0x06 */ + env_boot_osflags, /* 0x07 */ + env_booted_osflags, /* 0x08 */ + env_boot_reset, /* 0x09 */ + env_dump_dev, /* 0x0A */ + env_enable_audit, /* 0x0B */ + env_license, /* 0x0C */ + env_char_set, /* 0x0D */ + (char *)&env_language, /* 0x0E */ + env_tty_dev, /* 0x0F */ + 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x10 - 0x1F */ + 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x20 - 0x2F */ + 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x30 - 0x3F */ + 0, /* 0x40 */ + 0, /* 0x41 */ + env_scsiid, /* 0x42 */ + env_scsifast, /* 0x43 */ + env_com1_baud, /* 0x44 */ + env_com1_modem, /* 0x45 */ + env_com1_flow, /* 0x46 */ + env_com1_misc, /* 0x47 */ + env_com2_baud, /* 0x48 */ + env_com2_modem, /* 0x49 */ + env_com2_flow, /* 0x4A */ + env_com2_misc, /* 0x4B */ + env_password, /* 0x4C */ + env_secure, /* 0x4D */ + env_logfail, /* 0x4E */ + env_srm2dev_id, /* 0x4F */ + 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x50 - 0x5F */ + 0, /* 0x60 */ + 0, /* 0x61 */ + 0, /* 0x62 */ + 0, /* 0x63 */ +}; + +long +CallBackDispatcher(long a0, long a1, long a2, long a3, long a4) +{ + long i; + switch (a0) { + case CONSCB_GETC: + return GetChar(); + + case CONSCB_PUTS: + for (i = 0; i < a3; i++) + PutChar(*((char *)a2 + i)); + return a3; + + case CONSCB_GETENV: + if (a1 >= 0 && a1 < MAX_ENV_INDEX && envptr[a1] != 0 && *envptr[a1]) { + i = strcpy((char*)a2, envptr[a1]); + } else { + strcpy((char*)a2, ""); + i = (long)0xc000000000000000; + if (a1 >= 0 && a1 < MAX_ENV_INDEX) + printf_lock("GETENV unsupported option %d (0x%x)\n", a1, a1); + else + printf_lock("GETENV unsupported option %s\n", a1); + } + + if (i > a3) + panic("CONSCB_GETENV overwrote buffer\n"); + return i; + + case CONSCB_OPEN: + bcopy((char*)a1, deviceState[numOpenDevices].name, a2); + deviceState[numOpenDevices].name[a2] = '\0'; + printf_lock("CONSOLE OPEN : %s --> success \n", + deviceState[numOpenDevices].name); + return numOpenDevices++; + + case CONSCB_READ: + DeviceOperation(a0, a1, a2, a3, a4); + break; + + case CONSCB_CLOSE: + break; + + case CONSCB_OPEN_CONSOLE: + printf_lock("CONSOLE OPEN\n"); + return 0; /* success */ + break; /* not reached */ + + case CONSCB_CLOSE_CONSOLE: + printf_lock("CONSOLE CLOSE\n"); + return 0; /* success */ + break; /* not reached */ + + default: + panic("CallBackDispatcher(%x,%x,%x,%x,%x)\n", a0, a1, a2, a3, a4); + } + + return 0; +} + +long +CallBackFixup(int a0, int a1, int a2) +{ + long temp; + /* + * Linux uses r8 for the current pointer (pointer to data + * structure contating info about currently running process). It + * is set when the kernel starts and is expected to remain + * there... Problem is that the unlike the kernel, the console + * does not prevent the assembler from using r8. So here is a work + * around. So far this has only been a problem in CallBackFixup() + * but any other call back functions couldd cause a problem at + * some point + */ + + /* save off the current pointer to a temp variable */ + asm("bis $8, $31, %0" : "=r" (temp)); + + /* call original code */ + printf_lock("CallbackFixup %x %x, t7=%x\n", a0, a1, temp); + + /* restore the current pointer */ + asm("bis %0, $31, $8" : : "r" (temp) : "$8"); + + return 0; +} + +void +SlaveCmd(int cpu, struct rpb_percpu *my_rpb) +{ + extern ulong palJToSlave[]; + + printf_lock("Slave CPU %d console command %s", cpu, + my_rpb->rpb_iccb.iccb_rxbuf); + + my_rpb->rpb_state |= STATE_BIP; + my_rpb->rpb_state &= ~STATE_RC; + + printf_lock("SlaveCmd: restart %x %x vptb %x my_rpb %x my_rpb_phys %x\n", + rpb->rpb_restart, rpb->rpb_restart_pv, rpb->rpb_vptb, my_rpb, + KSEG_TO_PHYS(my_rpb)); + + cServe(KSEG_TO_PHYS(palJToSlave), (ulong)rpb->rpb_restart, + CSERVE_K_JTOPAL, rpb->rpb_restart_pv, rpb->rpb_vptb, + KSEG_TO_PHYS(my_rpb)); + + panic("SlaveCmd returned \n"); +} + +void +SlaveLoop(int cpu) +{ + int size = ROUNDUP128(sizeof(struct rpb_percpu)); + struct rpb_percpu *my_rpb = (struct rpb_percpu*) + ((ulong)rpb_percpu + size * cpu); + + if (cpu == 0) { + panic("CPU 0 entering slaveLoop. Reenetering the console. HOSED\n"); + } else { + printf_lock("Entering slaveloop for cpu %d my_rpb=%x\n", cpu, my_rpb); + } + + // swap the processors context to the one in the + // rpb_percpu struct very carefully (i.e. no stack usage) + // so that linux knows which processor ends up in __smp_callin + // and we don't trash any data is the process + SlaveSpin(cpu, my_rpb, &my_rpb->rpb_iccb.iccb_rxlen); +} diff --git a/system/alpha/console/dbmentry.S b/system/alpha/console/dbmentry.S new file mode 100644 index 0000000000..56a2c1950b --- /dev/null +++ b/system/alpha/console/dbmentry.S @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Debug Monitor Entry code + */ +#include "fromHudsonOsf.h" + + .extern myAlphaAccess + .text + +/* return address and padding to octaword align */ +#define STARTFRM 16 + + .globl _start + .ent _start, 0 +_start: +_entry: + br t0, 2f # get the current PC +2: ldgp gp, 0(t0) # init gp + +/* Processor 0 start stack frame is begining of physical memory (0) + Other processors spin here waiting to get their stacks from + Processor 0, then they can progress as normal. +*/ + call_pal PAL_WHAMI_ENTRY + beq v0, cpuz + ldq t3, m5AlphaAccess + addq t3,0x70,t3 # *** If offset in console alpha access struct changes + # This must be changed as well! + bis zero,8,t4 + mulq t4,v0,t4 + addq t3,t4,t3 + ldah a0, 3(zero) # load arg0 with 65536*3 +cpuwait: .long 0x6000002 # jsr quiesceNs + ldq t4, 0(t3) + beq t4, cpuwait + bis t4,t4,sp + + +cpuz: bis sp,sp,s0 /* save sp */ + +slave: lda v0,(8*1024)(sp) /* end of page */ + + subq zero, 1, t0 + sll t0, 42, t0 + bis t0, v0, sp + + lda sp, -STARTFRM(sp) # Create a stack frame + stq ra, 0(sp) # Place return address on the stack + + .mask 0x84000000, -8 + .frame sp, STARTFRM, ra + +/* + * Enable the Floating Point Unit + */ + lda a0, 1(zero) + call_pal PAL_WRFEN_ENTRY + +/* + * Every good C program has a main() + */ + +/* If stack pointer was 0, then this is CPU0*/ + beq s0,master + + call_pal PAL_WHAMI_ENTRY + bis v0,v0,a0 + jsr ra, SlaveLoop +master: + jsr ra, main + + + +/* + * The Debug Monitor should never return. + * However, just incase... + */ + ldgp gp, 0(ra) + bsr zero, _exit + +.end _start + + + + .globl _exit + .ent _exit, 0 +_exit: + + ldq ra, 0(sp) # restore return address + lda sp, STARTFRM(sp) # prune back the stack + ret zero, (ra) # Back from whence we came +.end _exit + + .globl cServe + .ent cServe 2 +cServe: + .option O1 + .frame sp, 0, ra + call_pal PAL_CSERVE_ENTRY + ret zero, (ra) + .end cServe + + .globl wrfen + .ent wrfen 2 +wrfen: + .option O1 + .frame sp, 0, ra + call_pal PAL_WRFEN_ENTRY + ret zero, (ra) + .end wrfen + .globl consoleCallback + .ent consoleCallback 2 +consoleCallback: + br t0, 2f # get the current PC +2: ldgp gp, 0(t0) # init gp + lda sp,-64(sp) + stq ra,0(sp) + jsr CallBackDispatcher + ldq ra,0(sp) + lda sp,64(sp) + ret zero,(ra) + .end consoleCallback + + + .globl consoleFixup + .ent consoleFixup 2 +consoleFixup: + br t0, 2f # get the current PC +2: ldgp gp, 0(t0) # init gp + lda sp,-64(sp) + stq ra,0(sp) + jsr CallBackFixup + ldq ra,0(sp) + lda sp,64(sp) + ret zero,(ra) + .end consoleFixup + + + + .globl SpinLock + .ent SpinLock 2 +SpinLock: +1: + ldq_l a1,0(a0) # interlock complete lock state + subl ra,3,v0 # get calling addr[31:0] + 1 + blbs a1,2f # branch if lock is busy + stq_c v0,0(a0) # attempt to acquire lock + beq v0,2f # branch if lost atomicity + mb # ensure memory coherence + ret zero,(ra) # return to caller (v0 is 1) +2: + br zero,1b + .end SpinLock + + .globl loadContext + .ent loadContext 2 +loadContext: + .option O1 + .frame sp, 0, ra + call_pal PAL_SWPCTX_ENTRY + ret zero, (ra) + .end loadContext + + + .globl SlaveSpin # Very carefully spin wait + .ent SlaveSpin 2 # and swap context without +SlaveSpin: # using any stack space + .option O1 + .frame sp, 0, ra + mov a0, t0 # cpu number + mov a1, t1 # cpu rpb pointer (virtual) + mov a2, t2 # what to spin on + ldah a0, 3(zero) # load arg0 with 65536 +test: .long 0x6000002 # jsr quiesceNs # wait 65us*3 + ldl t3, 0(t2) + beq t3, test + zapnot t1,0x1f,a0 # make rpb physical + call_pal PAL_SWPCTX_ENTRY # switch to pcb + mov t0, a0 # setup args for SlaveCmd + mov t1, a1 + jsr SlaveCmd # call SlaveCmd + ret zero, (ra) # Should never be reached + .end SlaveSpin + + diff --git a/system/alpha/console/paljtokern.S b/system/alpha/console/paljtokern.S new file mode 100644 index 0000000000..dfaf325331 --- /dev/null +++ b/system/alpha/console/paljtokern.S @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions +#include "ev5_defs.h" +#include "fromHudsonOsf.h" // OSF/1 specific definitions +#include "fromHudsonMacros.h" // Global macro definitions + +/* Jump to kernel + * args: + * Kernel address - a0 + * PCBB - a1 + * First free PFN - a3? + * + * Enable kseg addressing in ICSR + * Enable kseg addressing in MCSR + * Set VTBR -- Set to 1GB as per SRM, or maybe 8GB?? + * Set PCBB -- pass pointer in arg + * Set PTBR -- get it out of PCB + * Set KSP -- get it out of PCB + * + * Jump to kernel address + * + * Kernel args- + * s0 first free PFN + * s1 ptbr + * s2 argc 0 + * s3 argv NULL + * s5 osf_param (sysconfigtab) NULL + */ + + .global palJToKern + .text 3 +palJToKern: + ALIGN_BRANCH + + ldq_p a0, 0(zero) + ldq_p a1, 8(zero) + ldq_p a3, 16(zero) + + /* Point the Vptbr at 8GB */ + lda t0, 0x1(zero) + sll t0, 33, t0 + + mtpr t0, mVptBr // Load Mbox copy + mtpr t0, iVptBr // Load Ibox copy + STALL // don't dual issue the load with mtpr -pb + + /* Turn on superpage mapping in the mbox and icsr */ + lda t0, (2< + STALL // don't dual issue the load with mtpr -pb + mtpr t0, mcsr // Set the super page mode enable bit + STALL // don't dual issue the load with mtpr -pb + + lda t0, 0(zero) + mtpr t0, dtbAsn + mtpr t0, itbAsn + + LDLI (t1,0x20000000) + STALL // don't dual issue the load with mtpr -pb + mfpr t0, icsr // Enable superpage mapping + STALL // don't dual issue the load with mtpr -pb + bis t0, t1, t0 + mtpr t0, icsr + + STALL // Required stall to update chip ... + STALL + STALL + STALL + STALL + + ldq_p s0, PCB_Q_PTBR(a1) + sll s0, VA_S_OFF, s0 // Shift PTBR into position + STALL // don't dual issue the load with mtpr -pb + mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 + STALL // don't dual issue the load with mtpr -pb + ldq_p sp, PCB_Q_KSP(a1) + + mtpr a0, excAddr // Load the dispatch address. + STALL // don't dual issue the load with mtpr -pb + bis a3, zero, a0 // first free PFN + ldq_p a1, PCB_Q_PTBR(a1) // ptbr + ldq_p a2, 24(zero) // argc + ldq_p a3, 32(zero) // argv + ldq_p a4, 40(zero) // environ + lda a5, 0(zero) // osf_param + STALL // don't dual issue the load with mtpr -pb + mtpr zero, dtbIa // Flush all D-stream TB entries + mtpr zero, itbIa // Flush all I-stream TB entries + br zero, 2f + + ALIGN_BLOCK + +2: NOP + mtpr zero, icFlush // Flush the icache. + NOP + NOP + + NOP // Required NOPs ... 1-10 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 11-20 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 21-30 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 31-40 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 41-44 + NOP + NOP + NOP + + hw_rei_stall // Dispatch to kernel diff --git a/system/alpha/console/paljtoslave.S b/system/alpha/console/paljtoslave.S new file mode 100644 index 0000000000..59cfb210d3 --- /dev/null +++ b/system/alpha/console/paljtoslave.S @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions +#include "ev5_defs.h" +#include "fromHudsonOsf.h" // OSF/1 specific definitions +#include "fromHudsonMacros.h" // Global macro definitions + +/* + * args: + * a0: here + * a1: boot location + * a2: CSERVE_J_KTOPAL + * a3: restrart_pv + * a4: vptb + * a5: my_rpb + * + * SRM Console Architecture III 3-26 + */ + + .global palJToSlave + .text 3 +palJToSlave: + + ALIGN_BRANCH + + bis a3, zero, pv + bis zero, zero, t11 + bis zero, zero, ra + + /* Point the Vptbr to a2 */ + + mtpr a4, mVptBr // Load Mbox copy + mtpr a4, iVptBr // Load Ibox copy + STALL // don't dual issue the load with mtpr -pb + + /* Turn on superpage mapping in the mbox and icsr */ + lda t0, (2< + STALL // don't dual issue the load with mtpr -pb + mtpr t0, mcsr // Set the super page mode enable bit + STALL // don't dual issue the load with mtpr -pb + + lda t0, 0(zero) + mtpr t0, dtbAsn + mtpr t0, itbAsn + + LDLI (t1,0x20000000) + STALL // don't dual issue the load with mtpr -pb + mfpr t0, icsr // Enable superpage mapping + STALL // don't dual issue the load with mtpr -pb + bis t0, t1, t0 + mtpr t0, icsr + + STALL // Required stall to update chip ... + STALL + STALL + STALL + STALL + + ldq_p s0, PCB_Q_PTBR(a5) + sll s0, VA_S_OFF, s0 // Shift PTBR into position + STALL // don't dual issue the load with mtpr -pb + mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 + STALL // don't dual issue the load with mtpr -pb + ldq_p sp, PCB_Q_KSP(a5) + + mtpr zero, dtbIa // Flush all D-stream TB entries + mtpr zero, itbIa // Flush all I-stream TB entries + + mtpr a1, excAddr // Load the dispatch address. + + STALL // don't dual issue the load with mtpr -pb + STALL // don't dual issue the load with mtpr -pb + mtpr zero, dtbIa // Flush all D-stream TB entries + mtpr zero, itbIa // Flush all I-stream TB entries + br zero, 2f + + ALIGN_BLOCK + +2: NOP + mtpr zero, icFlush // Flush the icache. + NOP + NOP + + NOP // Required NOPs ... 1-10 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 11-20 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 21-30 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 31-40 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + NOP // Required NOPs ... 41-44 + NOP + NOP + NOP + + hw_rei_stall // Dispatch to kernel + diff --git a/system/alpha/console/printf.c b/system/alpha/console/printf.c new file mode 100644 index 0000000000..3d8cb41084 --- /dev/null +++ b/system/alpha/console/printf.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "m5op.h" + +/* The string s is terminated by a '\0' */ +void +PutString(const char *s) +{ + while (*s) + PutChar(*s++); +} + +/* print c count times */ +void +PutRepChar(char c, int count) +{ + while (count--) + PutChar(c); +} + +/* put string reverse */ +void +PutStringReverse(const char *s, int index) +{ + while (index-- > 0) + PutChar(s[index]); +} + +/* + * prints value in radix, in a field width width, with fill + * character fill + * if radix is negative, print as signed quantity + * if width is negative, left justify + * if width is 0, use whatever is needed + * if fill is 0, use ' ' + */ +void +PutNumber(long value, int radix, int width, char fill) +{ + char buffer[40]; + uint bufferindex = 0; + ulong uvalue; + ushort digit; + ushort left = 0; + ushort negative = 0; + + if (fill == 0) + fill = ' '; + + if (width < 0) { + width = -width; + left = 1; + } + + if (width < 0 || width > 80) + width = 0; + + if (radix < 0) { + radix = -radix; + if (value < 0) { + negative = 1; + value = -value; + } + } + + switch (radix) { + case 8: + case 10: + case 16: + break; + + default: + PutString("****"); + return; + } + + uvalue = value; + + do { + if (radix != 16) { + digit = (ushort)(uvalue % radix); + uvalue /= radix; + } else { + digit = (ushort)(uvalue & 0xf); + uvalue = uvalue >> 4; + } + buffer[bufferindex] = digit + ((digit <= 9) ? '0' : ('A' - 10)); + bufferindex += 1; + } while (uvalue != 0); + + /* fill # ' ' and negative cannot happen at once */ + if (negative) { + buffer[bufferindex] = '-'; + bufferindex += 1; + } + + if ((uint)width <= bufferindex) { + PutStringReverse(buffer, bufferindex); + } else { + width -= bufferindex; + if (!left) + PutRepChar(fill, width); + PutStringReverse(buffer, bufferindex); + if (left) + PutRepChar(fill, width); + } +} + +ulong +power(long base, long n) +{ + ulong p; + + for (p = 1; n > 0; --n) + p = p * base; + return p; +} + +void +putFloat(double a, int fieldwidth, char fill) +{ + int i; + ulong b; + + /* + * Put out everything before the decimal place. + */ + PutNumber(((ulong) a), 10, fieldwidth, fill); + + /* + * Output the decimal place. + */ + PutChar('.' & 0x7f); + + /* + * Output the n digits after the decimal place. + */ + for (i = 1; i < 6; i++) { + b = (ulong)(power(10, i) * (double)(a - (ulong) a)); + PutChar((char)(b % 10) + '0'); + } +} + +const char * +FormatItem(const char *f, va_list *ap) +{ + char c; + int fieldwidth = 0; + int leftjust = 0; + int radix = 0; + char fill = ' '; + + if (*f == '0') + fill = '0'; + + while (c = *f++) { + if (c >= '0' && c <= '9') { + fieldwidth = (fieldwidth * 10) + (c - '0'); + } else { + switch (c) { + case '\000': + return(--f); + case '%': + PutChar('%'); + return(f); + case '-': + leftjust = 1; + break; + case 'c': { + char a = (char)va_arg(*ap, int); + + if (leftjust) + PutChar(a & 0x7f); + if (fieldwidth > 0) + PutRepChar(fill, fieldwidth - 1); + if (!leftjust) + PutChar(a & 0x7f); + return(f); + } + case 's': { + const char *a = va_arg(*ap, const char *); + + if (leftjust) + PutString((const char *) a); + if (fieldwidth > strlen((const char *) a)) + PutRepChar(fill, fieldwidth - strlen((const char *)a)); + if (!leftjust) + PutString((const char *) a); + return(f); + } + case 'd': + radix = -10; + break; + case 'u': + radix = 10; + break; + case 'x': + radix = 16; + break; + case 'X': + radix = 16; + break; + case 'o': + radix = 8; + break; + case 'f': { + double a = va_arg(*ap, double); + + putFloat(a, fieldwidth, fill); + return(f); + } + default: /* unknown switch! */ + radix = 3; + break; + } + } + + if (radix) + break; + } + + if (leftjust) + fieldwidth = -fieldwidth; + + long a = va_arg(*ap, long); + PutNumber(a, radix, fieldwidth, fill); + + return(f); +} + +int +printf(const char *f, ...) +{ + va_list ap; + + va_start(ap, f); + + while (*f) { + if (*f == '%') + f = FormatItem(f + 1, &ap); + else + PutChar(*f++); + } + + if (*(f - 1) == '\n') { + /* add a line-feed (SimOS console output goes to shell */ + PutChar('\r'); + } + + va_end(ap); /* clean up */ + return 0; +} + +void +panic(const char *f, ...) +{ + va_list ap; + + va_start(ap, f); + + printf("CONSOLE PANIC (looping): "); + while (*f) { + if (*f == '%') + f = FormatItem(f + 1, &ap); + else + PutChar(*f++); + } + + va_end(ap); /* clean up */ + m5_panic(); +} diff --git a/system/alpha/h/cserve.h b/system/alpha/h/cserve.h new file mode 100644 index 0000000000..5b0e0f61c6 --- /dev/null +++ b/system/alpha/h/cserve.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define __CSERVE_LOADED 1 + +/* + * Console Service (cserve) sub-function codes: + */ +#define CSERVE_K_LDQP 0x01 +#define CSERVE_K_STQP 0x02 +#define CSERVE_K_JTOPAL 0x09 +#define CSERVE_K_WR_INT 0x0A +#define CSERVE_K_RD_IMPURE 0x0B +#define CSERVE_K_PUTC 0x0F +#define CSERVE_K_WR_ICSR 0x10 +#define CSERVE_K_WR_ICCSR 0x10 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_ICSR 0x11 +#define CSERVE_K_RD_ICCSR 0x11 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_BCCTL 0x12 +#define CSERVE_K_RD_BCCFG 0x13 + +#define CSERVE_K_WR_BCACHE 0x16 + +#define CSERVE_K_RD_BCCFG_OFF 0x17 +#define CSERVE_K_JTOKERN 0x18 + + diff --git a/system/alpha/h/dc21164FromGasSources.h b/system/alpha/h/dc21164FromGasSources.h new file mode 100644 index 0000000000..038861d360 --- /dev/null +++ b/system/alpha/h/dc21164FromGasSources.h @@ -0,0 +1,886 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DC21164FROMGASSOURCES_INCLUDED +#define DC21164FROMGASSOURCES_INCLUDED 1 + +/* +** +** INTERNAL PROCESSOR REGISTER DEFINITIONS +** +** The internal processor register definitions below are annotated +** with one of the following symbols: +** +** RW - The register may be read and written +** RO - The register may only be read +** WO - The register may only be written +** +** For RO and WO registers, all bits and fields within the register are +** also read-only or write-only. For RW registers, each bit or field +** within the register is annotated with one of the following: +** +** RW - The bit/field may be read and written +** RO - The bit/field may be read; writes are ignored +** WO - The bit/field may be written; reads return UNPREDICTABLE +** WZ - The bit/field may be written; reads return a zero value +** W0C - The bit/field may be read; write-zero-to-clear +** W1C - The bit/field may be read; write-one-to-clear +** WA - The bit/field may be read; write-anything-to-clear +** RC - The bit/field may be read, causing state to clear; +** writes are ignored +** +*/ + + +/* +** +** Ibox IPR Definitions: +** +*/ + +// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ +#define itbTag 0x101 /* WO - ITB Tag */ +#define itbPte 0x102 /* RW - ITB Page Table Entry */ +#define itbAsn 0x103 /* RW - ITB Address Space Number */ +#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ +#define itbIa 0x105 /* WO - ITB Invalidate All */ +#define itbIap 0x106 /* WO - ITB Invalidate All Process */ +#define itbIs 0x107 /* WO - ITB Invalidate Single */ +// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ +// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ +// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ +#define excAddr 0x10B /* RW - Exception Address */ +#define excSum 0x10C /* RW - Exception Summary */ +#define excMask 0x10D /* RO - Exception Mask */ +#define palBase 0x10E /* RW - PAL Base */ +#define ips 0x10F /* RW - Processor Status */ +// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ +#define intId 0x111 /* RO - Interrupt ID */ +#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ +#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ +#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ +#define slXmit 0x116 /* WO - Serial Line Transmit */ +#define slRcv 0x117 /* RO - Serial Line Receive */ +// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ +#define icFlush 0x119 /* WO - I-Cache Flush Control */ +#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ +#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ +#define PmCtr 0x11C /* RW - Performance Counter */ + +/* +** +** Ibox Control/Status Register (ICSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <39> 1 TST RW,0 Assert Test Status +** <38> 1 ISTA RO I-Cache BIST Status +** <37> 1 DBS RW,1 Debug Port Select +** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity +** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity +** <34> 1 FMS RW,0 Force I-Cache Miss +** <33> 1 SLE RW,0 Enable Serial Line Interrupts +** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts +** <30> 1 SDE RW,0 Enable PAL Shadow Registers +** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode +** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode +** <26> 1 FPE RW,0 Enable Floating Point Instructions +** <25> 1 TMD RW,0 Disable Ibox Timeout Counter +** <24> 1 TMM RW,0 Timeout Counter Mode +** +*/ + +#define ICSR_V_TST 39 +#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data +** +*/ + +#define SLXMIT_V_TMT 7 +#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data +** +*/ + +#define SLRCV_V_RCV 6 +#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error +** <12> 1 TPE W1C Tag parity error +** <11> 1 DPE W1C Data parity error +** +*/ + +#define ICPERR_V_TMR 13 +#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow +** <15> 1 INE WA Inexact result +** <14> 1 UNF WA Underflow +** <13> 1 FOV WA Overflow +** <12> 1 DZE WA Division by zero +** <11> 1 INV WA Invalid operation +** <10> 1 SWC WA Software completion +** +*/ + +#define EXC_V_IOV 16 +#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt +** <32> 1 CRDC W1C Clear Correctable Read Data interrupt +** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt +** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt +** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt +** +*/ + +#define HWINT_V_SLC 33 +#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt +** <33> 1 SLI RO Serial Line interrupt +** <32> 1 CRD RO Correctable ECC errors +** <31> 1 MCK RO System Machine Check +** <30> 1 PFL RO Power Fail +** <29> 1 PC2 RO Performance Counter 2 interrupt +** <28> 1 PC1 RO Performance Counter 1 interrupt +** <27> 1 PC0 RO Performance Counter 0 interrupt +** <23> 1 I23 RO External Hardware interrupt +** <22> 1 I22 RO External Hardware interrupt +** <21> 1 I21 RO External Hardware interrupt +** <20> 1 I20 RO External Hardware interrupt +** <19> 1 ATR RO Async. System Trap request +** <18:4> 15 SIRR RO,0 Software Interrupt request +** <3:0> 4 ASTRR RO Async. System Trap request (USEK) +** +**/ + +#define ISR_V_HLT 34 +#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction +** <10:06> 5 RA RO Ra field of faulting instruction +** <5> 1 BAD_VA RO Bad virtual address +** <4> 1 DTB_MISS RO Reference resulted in DTB miss +** <3> 1 FOW RO Fault on write +** <2> 1 FOR RO Fault on read +** <1> 1 ACV RO Access violation +** <0> 1 WR RO Reference type +** +*/ + +#define MMSTAT_V_OPC 11 +#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select +** <4> 1 E_BE RW,0 Ebox Big Endian mode enable +** <3> 1 DBG0 RW,0 Debug Test Select +** <2:1> 2 SP RW,0 Superpage mode enable +** <0> 1 M_BE RW,0 Mbox Big Endian mode enable +** +*/ + +#define MCSR_V_DBG1 5 +#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error +** <4> 1 TP0 RO Dcache bank 0 tag parity error +** <3> 1 DP1 RO Dcache bank 1 data parity error +** <2> 1 DP0 RO Dcache bank 0 data parity error +** <1> 1 LOCK W1C Locks/clears bits <5:2> +** <0> 1 SEO W1C Second Dcache parity error occurred +** +*/ + +#define DCPERR_V_TP1 5 +#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable +** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting +** <2> 1 BAD_DP RW,0 Force Dcache data bad parity +** <1> 1 FHIT RW,0 Force Dcache hit +** <0> 1 ENA RW,0 Software Dcache Enable +** +*/ + +#define DC_V_DOA 4 +#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request +** <6> 1 DREAD RO,0 If set, pending D-read request +** +*/ + +#define MAF_V_WB_PENDING 7 +#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable +** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select +** <11:08> 4 FB_DP RW,0 Force bad data parity +** <07:02> 6 TAG_STAT RW Tag status and parity +** <1> 1 FLUSH RW,0 If set, clear all tag valid bits +** <0> 1 FHIT RW,0 Force hits +** +*/ + +#define SC_V_SET_EN 13 +#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer +** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads +** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select +** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select +** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining +** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins +** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error +** <14:13> 2 BC_BAD_DAT WO,0 Force bad data +** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity +** <7> 1 BC_FHIT WO,0 Bcache force hit +** <6> 1 EI_ECC WO,1 ECC or byte parity mode +** <5> 1 VTM_FIRST WO,1 Drive out victim block address first +** <4> 1 CORR_FILL_DAT WO,1 Correct fill data +** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins +** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins +** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. +** <0> 1 BC_ENA W0,0 Bcache enable +** +*/ +#define BC_V_DIS_SC_VIC_BUF 27 +#define BC_M_DIS_SC_VIC_BUF (1<>1) +/* +** +** Bcache Configuration Register (BC_CONFIG) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <35:29> 7 RSVD WO Reserved - Must Be Zero +** <28:20> 9 WE_CTL WO,0 Bcache write enable control +** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero +** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset +** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero +** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing +** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles +** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles +** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero +** <02:00> 3 SIZE WO,1 Bcache size +*/ +#define BC_V_WE_CTL 20 +#define BC_M_WE_CTL (0x1FF< = 1. +*/ + +#define p0 r8 /* ITB/DTB Miss Scratch */ +#define p1 r9 /* ITB/DTB Miss Scratch */ +#define p2 r10 /* ITB/DTB Miss Scratch */ +#define p3 r11 +// #define ps r11 /* Processor Status */ +#define p4 r12 /* Local Scratch */ +#define p5 r13 /* Local Scratch */ +#define p6 r14 /* Local Scratch */ +#define p7 r25 /* Local Scratch */ + +/* +** SRM Defined State Definitions: +*/ + +/* +** This table is an accounting of the DECchip 21164 storage used to +** implement the SRM defined state for OSF/1. +** +** IPR Name Internal Storage +** -------- ---------------- +** Processor Status ps, dtbCm, ipl, r11 +** Program Counter Ibox +** Interrupt Entry ptEntInt +** Arith Trap Entry ptEntArith +** MM Fault Entry ptEntMM +** Unaligned Access Entry ptEntUna +** Instruction Fault Entry ptEntIF +** Call System Entry ptEntSys +** User Stack Pointer ptUsp +** Kernel Stack Pointer ptKsp +** Kernel Global Pointer ptKgp +** System Value ptSysVal +** Page Table Base Register ptPtbr +** Virtual Page Table Base iVptBr, mVptBr +** Process Control Block Base ptPcbb +** Address Space Number itbAsn, dtbAsn +** Cycle Counter cc, ccCtl +** Float Point Enable icsr +** Lock Flag Cbox/System +** Unique PCB +** Who-Am-I ptWhami +*/ + +#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ +#define ptImpure pt3 /* Pointer To PAL Scratch Area */ +#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ +#define ptIntMask pt8 /* Interrupt Enable Mask */ +#define ptEntSys pt9 /* Call System Dispatch Entry */ +#define ptTrap pt11 +#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ +#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ +#if defined(KDEBUG) +#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ +#endif /* KDEBUG */ +#define ptMisc pt16 /* Miscellaneous Flags */ +#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ +#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ +#define ptSysVal pt17 /* Per-Processor System Value */ +#define ptUsp pt18 /* User Stack Pointer */ +#define ptKsp pt19 /* Kernel Stack Pointer */ +#define ptPtbr pt20 /* Page Table Base Register */ +#define ptEntMM pt21 /* MM Fault Dispatch Entry */ +#define ptKgp pt22 /* Kernel Global Pointer */ +#define ptPcbb pt23 /* Process Control Block Base */ + +/* +** +** Miscellaneous PAL State Flags (ptMisc) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <55:48> 8 SWAP Swap PALcode flag -- character 'S' +** <47:32> 16 MCHK Machine Check Error code +** <31:16> 16 SCB System Control Block vector +** <15:08> 8 WHAMI Who-Am-I identifier +** <04:00> 5 MCES Machine Check Error Summary bits +** +*/ + +#define PT16_V_MCES 0 +#define PT16_V_WHAMI 8 +#define PT16_V_SCB 16 +#define PT16_V_MCHK 32 +#define PT16_V_SWAP 48 + +#endif /* DC21164FROMGASSOURCES_INCLUDED */ diff --git a/system/alpha/h/ev5_alpha_defs.h b/system/alpha/h/ev5_alpha_defs.h new file mode 100644 index 0000000000..d0264a4ca9 --- /dev/null +++ b/system/alpha/h/ev5_alpha_defs.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_ALPHA_DEFS_INCLUDED +#define EV5_ALPHA_DEFS_INCLUDED 1 + +// from ev5_alpha_defs.mar from Lance's fetch directory +// Lower-caseified and $ signs removed ... pb Nov/95 + +// +// PS Layout - PS +// Loc Size name function +// ------ ------ ______ ----------------------------------- +// <31:29> 3 SA stack alignment +// <31:13> 24 RES Reserved MBZ +// <12:8> 5 IPL Priority level +// <7> 1 VMM Virtual Mach Monitor +// <6:5> 2 RES Reserved MBZ +// <4:3> 2 CM Current Mode +// <2> 1 IP Interrupt Pending +// <1:0> 2 SW Software bits +// + +#define ps_v_sw 0 +#define ps_m_sw (3< 32 PFN Page Frame Number +// <31:16> 16 SOFT Bits reserved for software use +// <15> 1 UWE User write enable +// <14> 1 SWE Super write enable +// <13> 1 EWE Exec write enable +// <12> 1 KWE Kernel write enable +// <11> 1 URE User read enable +// <10> 1 SRE Super read enable +// <9> 1 ERE Exec read enable +// <8> 1 KRE Kernel read enable +// <7:6> 2 RES Reserved SBZ +// <5> 1 HPF Huge Page Flag +// <4> 1 ASM Wild card address space number match +// <3> 1 FOE Fault On execute +// <2> 1 FOW Fault On Write +// <1> 1 FOR Fault On Read +// <0> 1 V valid bit +// + +#define pte_v_pfn 32 +#define pte_m_soft (0xFFFF0000) +#define pte_v_soft 16 +#define pte_m_uwe (0x8000) +#define pte_v_uwe 15 +#define pte_m_swe (0x4000) +#define pte_v_swe 14 +#define pte_m_ewe (0x2000) +#define pte_v_ewe 13 +#define pte_m_kwe (0x1000) +#define pte_v_kwe 12 +#define pte_m_ure (0x0800) +#define pte_v_ure 11 +#define pte_m_sre (0x0400) +#define pte_v_sre 10 +#define pte_m_ere (0x0200) +#define pte_v_ere 9 +#define pte_m_kre (0x0100) +#define pte_v_kre 8 +#define pte_m_hpf (0x0020) +#define pte_v_hpf 5 +#define pte_m_asm (0x0010) +#define pte_v_asm 4 +#define pte_m_foe (0x0008) +#define pte_v_foe 3 +#define pte_m_fow (0x0004) +#define pte_v_fow 2 +#define pte_m_for (0x0002) +#define pte_v_for 1 +#define pte_m_v (0x0001) +#define pte_v_v 0 + +// +// VA layout - symbol prefix VA_ +// +// Loc Size name function +// ------ ------ ------- ----------------------------------- +// <42:33> 10 SEG1 First seg table offset for mapping +// <32:23> 10 SEG2 Second seg table offset for mapping +// <22:13> 10 SEG3 Third seg table offset for mapping +// <12:0> 13 OFFSET Byte within page +// + +#define va_m_offset (0x000000001FFF) +#define va_v_offset 0 +#define va_m_seg3 (0x0000007FE000) +#define va_v_seg3 13 +#define va_m_seg2 (0x0001FF800000) +#define va_v_seg2 23 +#define va_m_seg1 (0x7FE00000000) +#define va_v_seg1 33 + +// +//PRIVILEGED CONTEXT BLOCK (PCB) +// +#define pcb_q_ksp 0 +#define pcb_q_esp 8 +#define pcb_q_ssp 16 +#define pcb_q_usp 24 +#define pcb_q_ptbr 32 +#define pcb_q_asn 40 +#define pcb_q_ast 48 +#define pcb_q_fen 56 +#define pcb_q_cc 64 +#define pcb_q_unq 72 +#define pcb_q_sct 80 + +#define pcb_v_asten 0 +#define pcb_m_asten (0x0f< ; Software completion +// exs_v_inv <1> ; Ivalid operation +// exs_v_dze <2> ; Div by zero +// exs_v_fov <3> ; Floating point overflow +// exs_v_unf <4> ; Floating point underflow +// exs_v_ine <5> ; Floating point inexact +// exs_v_iov <6> ; Floating convert to integer overflow +#define exs_v_swc 0 +#define exs_v_inv 1 +#define exs_v_dze 2 +#define exs_v_fov 3 +#define exs_v_unf 4 +#define exs_v_ine 5 +#define exs_v_iov 6 + +#define exs_m_swc (1< ; machine check in progress +// mces_v_sce <1> ; system correctable error +// mces_v_pce <2> ; processor correctable error +// mces_v_dpc <3> ; disable reporting of processor correctable errors +// mces_v_dsc <4> ; disable reporting of system correctable errors +#define mces_v_mchk 0 +#define mces_v_sce 1 +#define mces_v_pce 2 +#define mces_v_dpc 3 +#define mces_v_dsc 4 + +#define mces_m_mchk (1< = 1, dc_fhit = 0, dc_bad_parity = 0 +#define mcsr_v_big_endian 0 +#define mcsr_v_sp0 1 +#define mcsr_v_sp1 2 +#define mcsr_v_mbox_sel 3 +#define mcsr_v_e_big_endian 4 +#define mcsr_v_dbg_packet_sel 5 +#define dc_mode_v_dc_ena 0 +#define dc_mode_v_dc_fhit 1 +#define dc_mode_v_dc_bad_parity 2 +#define dc_mode_v_dc_perr_dis 3 +#define dc_mode_v_dc_doa 4 +#define maf_mode_v_maf_nomerge 0 +#define maf_mode_v_wb_flush_always 1 +#define maf_mode_v_wb_nomerge 2 +#define maf_mode_v_io_nomerge 3 +#define maf_mode_v_wb_cnt_disable 4 +#define maf_mode_v_maf_arb_disable 5 +#define maf_mode_v_dread_pending 6 +#define maf_mode_v_wb_pending 7 +// mbox and dcache registers, continued. +#define mm_stat_v_wr 0 +#define mm_stat_v_acv 1 +#define mm_stat_v_for 2 +#define mm_stat_v_fow 3 +#define mm_stat_v_dtb_miss 4 +#define mm_stat_v_bad_va 5 +#define mm_stat_s_ra 5 +#define mm_stat_v_ra 6 +#define mm_stat_s_opcode 6 +#define mm_stat_v_opcode 11 +#define mvptbr_s_vptb 31 +#define mvptbr_v_vptb 33 +#define va_form_s_va 30 +#define va_form_v_va 3 +#define va_form_s_vptb 31 +#define va_form_v_vptb 33 +#define va_form_nt_s_va 19 +#define va_form_nt_v_va 3 +//.endm + +#endif diff --git a/system/alpha/h/ev5_impure.h b/system/alpha/h/ev5_impure.h new file mode 100644 index 0000000000..88634a7ef0 --- /dev/null +++ b/system/alpha/h/ev5_impure.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_IMPURE_INCLUDED +#define EV5_IMPURE_INCLUDED + +// This uses the Hudson file format from "impure.h" but with the fields from +// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 + +// file: impure.sdl +// +// PAL impure scratch area and logout area data structure definitions for +// Alpha firmware. +// +// +// module $pal_impure; +// +// Edit Date Who Description +// ---- --------- --- --------------------- +// 1 7-Jul-93 JEM Initial Entry +// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area +// Delete mvptbr +// Calculate pal$logout from end of impure area +// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions +// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, +// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat, +// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat, +// ei_addr, fill_syn, ld_lock +// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be +// consistent with ev4 +// add cns$ipr_offset +// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. +// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant +// to mchk logout frame +// +// +// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file +//orig + +/* +** Macros for saving/restoring data to/from the PAL impure scratch +** area. +** +** The console save state area is larger than the addressibility +** of the HW_LD/ST instructions (10-bit signed byte displacement), +** so some adjustments to the base offsets, as well as the offsets +** within each base region, are necessary. +** +** The console save state area is divided into two segments; the +** CPU-specific segment and the platform-specific segment. The +** state that is saved in the CPU-specific segment includes GPRs, +** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved +** in the platform-specific segment. +** +** The impure pointer will need to be adjusted by a different offset +** value for each region within a given segment. The SAVE and RESTORE +** macros will auto-magically adjust the offsets accordingly. +** +*/ +//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) +#define SEXT10(X) ((X) & 0x3ff) +//#define SEXT10(X) (((X) << 55) >> 55) + +#define SAVE_GPR(reg,offset,base) \ + stq_p reg, (SEXT10(offset-0x200))(base) + +#define RESTORE_GPR(reg,offset,base) \ + ldq_p reg, (SEXT10(offset-0x200))(base) + + +#define SAVE_FPR(reg,offset,base) \ + stt reg, (SEXT10(offset-0x200))(base) + +#define RESTORE_FPR(reg,offset,base) \ + ldt reg, (SEXT10(offset-0x200))(base) + +#define SAVE_IPR(reg,offset,base) \ + mfpr v0, reg; \ + stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) + +#define RESTORE_IPR(reg,offset,base) \ + ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ + mtpr v0, reg + +#define SAVE_SHADOW(reg,offset,base) \ + stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) + +#define RESTORE_SHADOW(reg,offset,base)\ + ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) + +/* Structure of the processor-specific impure area */ + +/* aggregate impure struct prefix "" tag ""; + * cns$flag quadword; + * cns$hlt quadword; + */ + +/* Define base for debug monitor compatibility */ +#define CNS_Q_BASE 0x000 +#define CNS_Q_FLAG 0x100 +#define CNS_Q_HALT 0x108 + + +/* constant ( + * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, + * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, + * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, + * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 + * ) equals . increment 8 prefix "" tag ""; + * cns$gpr quadword dimension 32; + */ + +/* Offset to base of saved GPR area - 32 quadword */ +#define CNS_Q_GPR 0x110 +#define cns_gpr CNS_Q_GPR + +/* constant ( + * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, + * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, + * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, + * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 + * ) equals . increment 8 prefix "" tag ""; + * cns$fpr quadword dimension 32; + */ + +/* Offset to base of saved FPR area - 32 quadwords */ +#define CNS_Q_FPR 0x210 + +/* #t=.; + * cns$mchkflag quadword; + */ +#define CNS_Q_MCHK 0x310 + +/* constant cns$pt_offset equals .; + * constant ( + * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, + * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, + * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, + * cns$pt21,cns$pt22,cns$pt23 + * ) equals . increment 8 prefix "" tag ""; + * cns$pt quadword dimension 24; + */ +/* Offset to base of saved PALtemp area - 25 quadwords */ +#define CNS_Q_PT 0x318 + +/* cns$shadow8 quadword; + * cns$shadow9 quadword; + * cns$shadow10 quadword; + * cns$shadow11 quadword; + * cns$shadow12 quadword; + * cns$shadow13 quadword; + * cns$shadow14 quadword; + * cns$shadow25 quadword; + */ +/* Offset to base of saved PALshadow area - 8 quadwords */ +#define CNS_Q_SHADOW 0x3D8 + +/* Offset to base of saved IPR area */ +#define CNS_Q_IPR 0x418 + +/* constant cns$ipr_offset equals .; */ +/* cns$exc_addr quadword; */ +#define CNS_Q_EXC_ADDR 0x418 +/* cns$pal_base quadword; */ +#define CNS_Q_PAL_BASE 0x420 +/* cns$mm_stat quadword; */ +#define CNS_Q_MM_STAT 0x428 +/* cns$va quadword; */ +#define CNS_Q_VA 0x430 +/* cns$icsr quadword; */ +#define CNS_Q_ICSR 0x438 +/* cns$ipl quadword; */ +#define CNS_Q_IPL 0x440 +/* cns$ps quadword; // Ibox current mode */ +#define CNS_Q_IPS 0x448 +/* cns$itb_asn quadword; */ +#define CNS_Q_ITB_ASN 0x450 +/* cns$aster quadword; */ +#define CNS_Q_ASTER 0x458 +/* cns$astrr quadword; */ +#define CNS_Q_ASTRR 0x460 +/* cns$isr quadword; */ +#define CNS_Q_ISR 0x468 +/* cns$ivptbr quadword; */ +#define CNS_Q_IVPTBR 0x470 +/* cns$mcsr quadword; */ +#define CNS_Q_MCSR 0x478 +/* cns$dc_mode quadword; */ +#define CNS_Q_DC_MODE 0x480 +/* cns$maf_mode quadword; */ +#define CNS_Q_MAF_MODE 0x488 +/* cns$sirr quadword; */ +#define CNS_Q_SIRR 0x490 +/* cns$fpcsr quadword; */ +#define CNS_Q_FPCSR 0x498 +/* cns$icperr_stat quadword; */ +#define CNS_Q_ICPERR_STAT 0x4A0 +/* cns$pmctr quadword; */ +#define CNS_Q_PM_CTR 0x4A8 +/* cns$exc_sum quadword; */ +#define CNS_Q_EXC_SUM 0x4B0 +/* cns$exc_mask quadword; */ +#define CNS_Q_EXC_MASK 0x4B8 +/* cns$intid quadword; */ +#define CNS_Q_INT_ID 0x4C0 +/* cns$dcperr_stat quadword; */ +#define CNS_Q_DCPERR_STAT 0x4C8 +/* cns$sc_stat quadword; */ +#define CNS_Q_SC_STAT 0x4D0 +/* cns$sc_addr quadword; */ +#define CNS_Q_SC_ADDR 0x4D8 +/* cns$sc_ctl quadword; */ +#define CNS_Q_SC_CTL 0x4E0 +/* cns$bc_tag_addr quadword; */ +#define CNS_Q_BC_TAG_ADDR 0x4E8 +/* cns$ei_stat quadword; */ +#define CNS_Q_EI_STAT 0x4F0 +/* cns$ei_addr quadword; */ +#define CNS_Q_EI_ADDR 0x4F8 +/* cns$fill_syn quadword; */ +#define CNS_Q_FILL_SYN 0x500 +/* cns$ld_lock quadword; */ +#define CNS_Q_LD_LOCK 0x508 +/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */ +#define CNS_Q_BC_CTL 0x510 +/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ +#define CNS_Q_PM_CTL 0x518 +/* cns$bc_config quadword; // shadow of on chip bc_config */ +#define CNS_Q_BC_CFG 0x520 + +/* constant cns$size equals .; + * + * constant pal$impure_common_size equals (%x0200 +7) & %xfff8; + * constant pal$impure_specific_size equals (.+7) & %xfff8; + * constant cns$mchksize equals (.+7-#t) & %xfff8; + * constant pal$logout_area equals pal$impure_specific_size ; + * end impure; +*/ + +/* This next set of stuff came from the old code ..pb */ +#define CNS_Q_SROM_REV 0x528 +#define CNS_Q_PROC_ID 0x530 +#define CNS_Q_MEM_SIZE 0x538 +#define CNS_Q_CYCLE_CNT 0x540 +#define CNS_Q_SIGNATURE 0x548 +#define CNS_Q_PROC_MASK 0x550 +#define CNS_Q_SYSCTX 0x558 + + + +#define MACHINE_CHECK_CRD_BASE 0 +#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) + + + +/* + * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; + * SPROCESS bitfield length 1 ; + * FILL_0 bitfield length 3 fill tag $$; + * FRQ2 bitfield length 2 ; + * FRQ1 bitfield length 2 ; + * FRQ0 bitfield length 2 ; + * CTL2 bitfield length 2 ; + * CTL1 bitfield length 2 ; + * CTL0 bitfield length 2 ; + * FILL_1 bitfield length 16 fill tag $$; + * FILL_2 bitfield length 32 fill tag $$; + * end EV5PMCTRCTL_BITS; + * + * end_module $pal_impure; + * + * module $pal_logout; + * + * // + * // Start definition of Corrected Error Frame + * // + */ + +/* + * aggregate crd_logout struct prefix "" tag ""; + */ + +#define pal_logout_area 0x600 +#define mchk_crd_base 0 + +/* mchk$crd_flag quadword; */ +#define mchk_crd_flag 0 +/* mchk$crd_offsets quadword; */ +#define mchk_crd_offsets 8 +/* + * // Pal-specific information */ +#define mchk_crd_mchk_code 0x10 +/* mchk$crd_mchk_code quadword; + * + * // CPU-specific information + * constant mchk$crd_cpu_base equals . ; + * mchk$crd_ei_addr quadword; */ +#define mchk_crd_ei_addr 0x18 +/* mchk$crd_fill_syn quadword; */ +#define mchk_crd_fill_syn 0x20 +/* mchk$crd_ei_stat quadword; */ +#define mchk_crd_ei_stat 0x28 +/* mchk$crd_isr quadword; */ +#define mchk_crd_isr 0x30 + +/* + * Hacked up constants for the turbolaser build. Hope + * this is moreless correct + */ + +#define mchk_crd_whami 0x38 +#define mchk_crd_tldev 0x40 +#define mchk_crd_tlber 0x48 +#define mchk_crd_tlesr0 0x50 +#define mchk_crd_tlesr1 0x58 +#define mchk_crd_tlesr2 0x60 +#define mchk_crd_tlesr3 0x68 +#define mchk_crd_rsvd 0x70 + + +/* + * mchk area seems different for tlaser + */ + +#define mchk_crd_size 0x80 +#define mchk_mchk_base (mchk_crd_size) + +#define mchk_tlber 0x0 +#define mchk_tlepaerr 0x8 +#define mchk_tlepderr 0x10 +#define mchk_tlepmerr 0x18 + + +/* + * // System-specific information + * constant mchk$crd_sys_base equals . ; + * constant mchk$crd_size equals (.+7) & %xfff8; + * + * end crd_logout; + * // + * // Start definition of Machine check logout Frame + * // + * aggregate logout struct prefix "" tag ""; + * mchk$flag quadword; */ +/* mchk$offsets quadword; */ +/* + * // Pal-specific information + * mchk$mchk_code quadword; */ +/* + + * mchk$pt quadword dimension 24; + * + * // CPU-specific information + * constant mchk$cpu_base equals . ; + * mchk$exc_addr quadword; + * mchk$exc_sum quadword; + * mchk$exc_mask quadword; + * mchk$pal_base quadword; + * mchk$isr quadword; + * mchk$icsr quadword; + * mchk$ic_perr_stat quadword; + * mchk$dc_perr_stat quadword; + * mchk$va quadword; + * mchk$mm_stat quadword; + * mchk$sc_addr quadword; + * mchk$sc_stat quadword; + * mchk$bc_tag_addr quadword; + * mchk$ei_addr quadword; + * mchk$fill_syn quadword; + * mchk$ei_stat quadword; + * mchk$ld_lock quadword; + * + * // System-specific information + * + * constant mchk$sys_base equals . ; + * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff + * + * constant mchk$size equals (.+7) & %xfff8; + * + * + * constant mchk$crd_base equals 0 ; + * constant mchk$mchk_base equals mchk$crd_size ; + * + * + * end logout; + * + * end_module $pal_logout; +*/ + +/* + * this is lingering in the old ladbx code but looks like it was from + * ev4 days. This was 0x160 in the old days..pb + */ +#define LAF_K_SIZE MACHINE_CHECK_SIZE +#endif diff --git a/system/alpha/h/ev5_osfalpha_defs.h b/system/alpha/h/ev5_osfalpha_defs.h new file mode 100644 index 0000000000..bb98503b41 --- /dev/null +++ b/system/alpha/h/ev5_osfalpha_defs.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_OSFALPHA_DEFS_INCLUDED +#define EV5_OSFALPHA_DEFS_INCLUDED 1 + +// from ev5_osfalpha_defs.mar from Lance's fetch directory +// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95 + +// +// PS Layout - PS +// Loc Size name function +// ------ ------ ----- ----------------------------------- +// <0:2> 3 IPL Prio level +// <3> 1 CM Current Mode +// + +#define osfps_v_mode 3 +#define osfps_m_mode (1< 32 PFN Page Frame Number +// <31:16> 16 SOFT Bits reserved for software use +// <15:14> 2 +// <13> 1 UWE User write enable +// <12> 1 KWE Kernel write enable +// <11:10> 2 +// <9> 1 URE User read enable +// <8> 1 KRE Kernel read enable +// <7:6> 2 RES Reserved SBZ +// <5> 1 HPF Huge Page Flag +// <4> 1 ASM Wild card address space number match +// <3> 1 FOE Fault On execute +// <2> 1 FOW Fault On Write +// <1> 1 FOR Fault On Read +// <0> 1 V valid bit +// + +#define osfpte_v_pfn 32 +#define osfpte_m_soft (0xFFFF0000) +#define osfpte_v_soft 16 +#define osfpte_m_uwe (0x2000) +#define osfpte_v_uwe 13 +#define osfpte_m_kwe (0x1000) +#define osfpte_v_kwe 12 +#define osfpte_m_ure (0x0200) +#define osfpte_v_ure 9 +#define osfpte_m_kre (0x0100) +#define osfpte_v_kre 8 +#define osfpte_m_hpf (0x0020) +#define osfpte_v_hpf 5 +#define osfpte_m_asm (0x0010) +#define osfpte_v_asm 4 +#define osfpte_m_foe (0x0008) +#define osfpte_v_foe 3 +#define osfpte_m_fow (0x0004) +#define osfpte_v_fow 2 +#define osfpte_m_for (0x0002) +#define osfpte_v_for 1 +#define osfpte_m_v (0x0001) +#define osfpte_v_v 0 + +#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm) +#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe) + +// +// VA layout - symbol prefix VA_ +// +// Loc Size name function +// ------ ------ ------- ----------------------------------- +// <42:33> 10 SEG1 First seg table offset for mapping +// <32:23> 10 SEG2 Second seg table offset for mapping +// <22:13> 10 SEG3 Third seg table offset for mapping +// <12:0> 13 OFFSET Byte within page +// + +#define osfva_m_offset (0x000000001FFF) +#define osfva_v_offset 0 +#define osfva_m_seg3 (0x0000007FE000) +#define osfva_v_seg3 13 +#define osfva_m_seg2 (0x0001FF800000) +#define osfva_v_seg2 23 +#define osfva_m_seg1 (0x7FE00000000) +#define osfva_v_seg1 33 + +#define osfpcb_q_ksp (0x0000) +#define osfpcb_q_usp (0x0008) +#define osfpcb_q_Usp (0x0008) +#define osfpcb_q_mmptr (0x0010) +#define osfpcb_q_Mmptr (0x0010) +#define osfpcb_l_cc (0x0018) +#define osfpcb_l_asn (0x001C) +#define osfpcb_q_unique (0x0020) +#define osfpcb_q_fen (0x0028) +#define osfpcb_v_pme 62 + +#define osfsf_ps (0x00) +#define osfsf_pc (0x08) +#define osfsf_gp (0x10) +#define osfsf_a0 (0x18) +#define osfsf_a1 (0x20) +#define osfsf_a2 (0x28) +#define osfsf_c_size (0x30) + +#endif diff --git a/system/alpha/h/ev5_paldef.h b/system/alpha/h/ev5_paldef.h new file mode 100644 index 0000000000..49cea5faab --- /dev/null +++ b/system/alpha/h/ev5_paldef.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_PALDEF_INCLUDED +#define EV5_PALDEF_INCLUDED 1 + +// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95 +// some entries have been superceeded by the more recent evt_defs.h + +// These are lower-caseified and have the $ signs (unnecessarily we +// now discover) removed. + +// Note that at the bottom of this file is the version of ev5_defs.mar +// which is more recent than the top part of the file and contains +// overlapping information...pb Nov/95 + +#define hlt_c_reset 0 +#define hlt_c_hw_halt 1 +#define hlt_c_ksp_inval 2 +#define hlt_c_scbb_inval 3 +#define hlt_c_ptbr_inval 4 +#define hlt_c_sw_halt 5 +#define hlt_c_dbl_mchk 6 +#define hlt_c_mchk_from_pal 7 +#define hlt_c_start 32 +#define hlt_c_callback 33 +#define hlt_c_mpstart 34 +#define hlt_c_lfu_start 35 + +#define mchk_c_tperr (64<<1) +#define mchk_c_tcperr (65<<1) +#define mchk_c_herr (66<<1) +#define mchk_c_ecc_c (67<<1) +#define mchk_c_ecc_nc (68<<1) +#define mchk_c_unknown (69<<1) +#define mchk_c_cacksoft (70<<1) +#define mchk_c_bugcheck (71<<1) +#define mchk_c_os_bugcheck (72<<1) +#define mchk_c_dcperr (73<<1) +#define mchk_c_icperr (74<<1) +#define mchk_c_retryable_ird (75<<1) +#define mchk_c_proc_hrd_error (76<<1) +#define mchk_c_scperr (77<<1) +#define mchk_c_bcperr (78<<1) +//; mchk codes above 255 reserved for platform specific errors + + +#define mchk_c_read_nxm (256<<1) +#define mchk_c_sys_hrd_error (257<<1) +#define mchk_c_sys_ecc (258<<1) + +#define page_seg_size_bits 10 +#define page_offset_size_bits 13 +#define page_size_bytes 8192 +#define va_size_bits 43 +#define pa_size_bits 45 + +// replaced by ev5_defs.h #define pt0 (0x140) +// replaced by ev5_defs.h #define pt1 (0x141) +// replaced by ev5_defs.h #define pt2 (0x142) +#define pt_entuna (0x142) +// replaced by ev5_defs.h #define pt3 (0x143) +#define pt_impure (0x143) +// replaced by ev5_defs.h #define pt4 (0x144) +// replaced by ev5_defs.h #define pt5 (0x145) +// replaced by ev5_defs.h #define pt6 (0x146) +// replaced by ev5_defs.h #define pt7 (0x147) +#define pt_entif (0x147) +// replaced by ev5_defs.h #define pt8 (0x148) +#define pt_intmask (0x148) +// replaced by ev5_defs.h #define pt9 (0x149) +#define pt_entsys (0x149) +#define pt_ps (0x149) +// replaced by ev5_defs.h #define pt10 (0x14a) +// replaced by ev5_defs.h #define pt11 (0x14b) +#define pt_trap (0x14b) +#define pt_entint (0x14b) +// replaced by ev5_defs.h #define pt12 (0x14c) +#define pt_entarith (0x14c) +// replaced by ev5_defs.h #define pt13 (0x14d) +#define pt_sys0 (0x14d) +// replaced by ev5_defs.h #define pt14 (0x14e) +#define pt_sys1 (0x14e) +// replaced by ev5_defs.h #define pt15 (0x14f) +#define pt_sys2 (0x14f) +// replaced by ev5_defs.h #define pt16 (0x150) +#define pt_whami (0x150) +#define pt_mces (0x150) +#define pt_misc (0x150) +// replaced by ev5_defs.h #define pt17 (0x151) +#define pt_scc (0x151) +#define pt_sysval (0x151) +// replaced by ev5_defs.h #define pt18 (0x152) +#define pt_prbr (0x152) +#define pt_usp (0x152) +// replaced by ev5_defs.h #define pt19 (0x153) +#define pt_ksp (0x153) +// replaced by ev5_defs.h #define pt20 (0x154) +#define pt_ptbr (0x154) +// replaced by ev5_defs.h #define pt21 (0x155) +#define pt_vptbr (0x155) +#define pt_entmm (0x155) +// replaced by ev5_defs.h #define pt22 (0x156) +#define pt_scbb (0x156) +#define pt_kgp (0x156) +// replaced by ev5_defs.h #define pt23 (0x157) +#define pt_pcbb (0x157) + + +#define pt_misc_v_switch 48 +#define pt_misc_v_cm 56 + +#define mmcsr_c_tnv 0 +#define mmcsr_c_acv 1 +#define mmcsr_c_for 2 +#define mmcsr_c_foe 3 +#define mmcsr_c_fow 4 + +#define mm_stat_m_opcode (0x3F) +#define mm_stat_m_ra (0x1F) +#define evx_opc_sync (0x18) +#define EVX_OPC_SYNC (0x18) +#define evx_opc_hw_ld (0x1B) + +#define osf_a0_bpt (0x0) +#define osf_a0_bugchk (0x1) +#define osf_a0_gentrap (0x2) +#define osf_a0_fen (0x3) +#define osf_a0_opdec (0x4) + +#define ipl_machine_check 31 +#define ipl_powerfail 30 +#define ipl_perf_count 29 +#define ipl_clock 22 +#define ipl_interprocessor 22 + +#endif diff --git a/system/alpha/h/fromHudsonMacros.h b/system/alpha/h/fromHudsonMacros.h new file mode 100644 index 0000000000..68f8999c05 --- /dev/null +++ b/system/alpha/h/fromHudsonMacros.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 1993-1994 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HUDSON_MACROS_LOADED +#define HUDSON_MACROS_LOADED 1 + +#define STALL \ + mfpr r31, pt0 + +#define NOP \ + bis $31, $31, $31 + +/* +** Align code on an 8K byte page boundary. +*/ + +#define ALIGN_PAGE \ + .align 13 + +/* +** Align code on a 32 byte block boundary. +*/ + +#define ALIGN_BLOCK \ + .align 5 + +/* +** Align code on a quadword boundary. +*/ + +#define ALIGN_BRANCH \ + .align 3 + +/* +** Hardware vectors go in .text 0 sub-segment. +*/ + +#define HDW_VECTOR(offset) \ + . = offset + +/* +** Privileged CALL_PAL functions are in .text 1 sub-segment. +*/ + +#define CALL_PAL_PRIV(vector) \ + . = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6)) + +/* +** Unprivileged CALL_PAL functions are in .text 1 sub-segment, +** the privileged bit is removed from these vectors. +*/ + +#define CALL_PAL_UNPRIV(vector) \ + . = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6)) + +/* +** Implements a load "immediate" longword function +*/ +#define LDLI(reg,val) \ + ldah reg, ((val+0x8000) >> 16)(zero); \ + lda reg, (val&0xffff)(reg) + +#endif diff --git a/system/alpha/h/fromHudsonOsf.h b/system/alpha/h/fromHudsonOsf.h new file mode 100644 index 0000000000..e1dfc8171d --- /dev/null +++ b/system/alpha/h/fromHudsonOsf.h @@ -0,0 +1,483 @@ +/* + * Copyright (c) 1993-1994 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FROMHUDSONOSF_INCLUDED +#define FROMHUDSONOSF_INCLUDED 1 + +#define __OSF_LOADED 1 +/* +** Seg0 and Seg1 Virtual Address (VA) Format +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <42:33> 10 SEG1 First level page table offset +** <32:23> 10 SEG2 Second level page table offset +** <22:13> 10 SEG3 Third level page table offset +** <12:00> 13 OFFSET Byte within page offset +*/ + +#define VA_V_SEG1 33 +#define VA_M_SEG1 (0x3FF< 32 PFN Page Frame Number +** <31:16> 16 SW Reserved for software +** <15:14> 2 RSV0 Reserved for hardware SBZ +** <13> 1 UWE User Write Enable +** <12> 1 KWE Kernel Write Enable +** <11:10> 2 RSV1 Reserved for hardware SBZ +** <9> 1 URE User Read Enable +** <8> 1 KRE Kernel Read Enable +** <7> 1 RSV2 Reserved for hardware SBZ +** <6:5> 2 GH Granularity Hint +** <4> 1 ASM Address Space Match +** <3> 1 FOE Fault On Execute +** <2> 1 FOW Fault On Write +** <1> 1 FOR Fault On Read +** <0> 1 V Valid +*/ + +#define PTE_V_PFN 32 +#define PTE_M_PFN 0xFFFFFFFF00000000 +#define PTE_V_SW 16 +#define PTE_M_SW 0x00000000FFFF0000 +#define PTE_V_UWE 13 +#define PTE_M_UWE (1< 1 CM Current Mode +** <2:0> 3 IPL Interrupt Priority Level +**/ + +#define PS_V_CM 3 +#define PS_M_CM (1< 1 MIP Machine check in progress +** <1> 1 SCE System correctable error in progress +** <2> 1 PCE Processor correctable error in progress +** <3> 1 DPC Disable PCE error reporting +** <4> 1 DSC Disable SCE error reporting +*/ + +#define MCES_V_MIP 0 +#define MCES_M_MIP (1< 8 ID Who-Am-I identifier +** <15:8> 1 SWAP Swap PALcode flag - character 'S' +*/ + +#define WHAMI_V_SWAP 8 +#define WHAMI_M_SWAP (1<rpb_ctb_off))) + +#define CRB_SETUP \ + ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off))) + +/* + * The "Dynamic System Recognition" portion of the HWRPB. + * It is used to obtain the platform specific data need to allow + * the platform define the platform name, the platform SMM and LURT + * data for software licensing + */ +struct rpb_dsr { + long rpb_smm; /* SMM nubber used by LMF */ + ulong rpb_lurt_off; /* offset to LURT table */ + ulong rpb_sysname_off; /* offset to sysname char count */ + int lurt[10]; /* XXM has one LURT entry */ +}; diff --git a/system/alpha/h/tlaser.h b/system/alpha/h/tlaser.h new file mode 100644 index 0000000000..283d61be3c --- /dev/null +++ b/system/alpha/h/tlaser.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1990 Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define tlsb_tlber 0x40 +#define tlsb_tldev 0x00 +#define tlsb_tlesr0 0x680 +#define tlsb_tlesr1 0x6C0 +#define tlsb_tlesr2 0x700 +#define tlsb_tlesr3 0x740 diff --git a/system/alpha/palcode/Makefile b/system/alpha/palcode/Makefile new file mode 100644 index 0000000000..2f1eded33f --- /dev/null +++ b/system/alpha/palcode/Makefile @@ -0,0 +1,92 @@ +# Copyright (c) 2003, 2004 +# The Regents of The University of Michigan +# All Rights Reserved +# +# This code is part of the M5 simulator. +# +# Permission is granted to use, copy, create derivative works and +# redistribute this software and such derivative works for any purpose, +# so long as the copyright notice above, this grant of permission, and +# the disclaimer below appear in all copies made; and so long as the +# name of The University of Michigan is not used in any advertising or +# publicity pertaining to the use or distribution of this software +# without specific, written prior authorization. +# +# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE +# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT +# WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR +# IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF +# THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES, +# INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION +# WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# +# Authors: Nathan L. Binkert +# Ali G. Saidi + +# Makefile for palcode +# Works on alpha-linux and builds elf executable + +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), alpha) +CROSS_COMPILE?=alpha-unknown-linux-gnu- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld + +CFLAGS=-I . -I ../h -nostdinc -nostdinc++ -Wa,-m21164 +LDFLAGS=-Ttext 0x4000 + +TLOBJS = osfpal.o platform_tlaser.o +TLOBJS_COPY = osfpal_cache_copy.o platform_tlaser.o +TLOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_tlaser.o +TSOBJS = osfpal.o platform_tsunami.o +TSBOBJS = osfpal.o platform_bigtsunami.o +TSOBJS_COPY = osfpal_cache_copy.o platform_tsunami.o +TSOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_bigtsunami.o + +all: tlaser tsunami tsunami_b64 + +all_copy: tlaser tlaser_copy tsunami tsunami_b64 tsunami_copy + +osfpal.o: osfpal.S + $(CC) $(CFLAGS) -o $@ -c $< + +osfpal_cache_copy.o: osfpal.S + $(CC) $(CFLAGS) -DCACHE_COPY -o $@ -c $< + +osfpal_cache_copy_unaligned.o: osfpal.S + $(CC) $(CFLAGS) -DCACHE_COPY -DCACHE_COPY_UNALIGNED -o $@ -c $< + +platform_tlaser.o: platform.S + $(CC) $(CFLAGS) -DTLASER -o $@ -c $< + +platform_tsunami.o: platform.S + $(CC) $(CFLAGS) -DTSUNAMI -o $@ -c $< + +platform_bigtsunami.o: platform.S + $(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $< + +tlaser: $(TLOBJS) + $(LD) $(LDFLAGS) -o tl_osfpal $(TLOBJS) + +tlaser_copy: $(TLOBJS_COPY) $(TLOBJS_COPY_UNALIGNED) + $(LD) $(LDFLAGS) -o tl_osfpal_cache $(TLOBJS_COPY) + $(LD) $(LDFLAGS) -o tl_osfpal_unalign $(TLOBJS_COPY_UNALIGNED) + +tsunami: $(TSOBJS) + $(LD) $(LDFLAGS) -o ts_osfpal $(TSOBJS) + +tsunami_b64: $(TSBOBJS) + $(LD) $(LDFLAGS) -o tsb_osfpal $(TSBOBJS) + +tsunami_copy: $(TSOBJS_COPY) $(TSOBJS_COPY_UNALIGNED) + $(LD) $(LDFLAGS) -o ts_osfpal_cache $(TSOBJS_COPY) + $(LD) $(LDFLAGS) -o ts_osfpal_unalign $(TSOBJS_COPY_UNALIGNED) + +clean: + rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \ + ts_osfpal_cache ts_osfpal_unalign tsb_osfpal diff --git a/system/alpha/palcode/osfpal.S b/system/alpha/palcode/osfpal.S new file mode 100644 index 0000000000..3ec4d40118 --- /dev/null +++ b/system/alpha/palcode/osfpal.S @@ -0,0 +1,4202 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * Copyright (c) 1992-1995 Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali G. Saidi + * Nathan L. Binkert + */ + +// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl +// since we don't have a mechanism to expand the data structures.... pb Nov/95 +#include "ev5_defs.h" +#include "ev5_impure.h" +#include "ev5_alpha_defs.h" +#include "ev5_paldef.h" +#include "ev5_osfalpha_defs.h" +#include "fromHudsonMacros.h" +#include "fromHudsonOsf.h" +#include "dc21164FromGasSources.h" + +#define DEBUGSTORE(c) nop + +#define DEBUG_EXC_ADDR()\ + bsr r25, put_exc_addr; \ + DEBUGSTORE(13) ; \ + DEBUGSTORE(10) + +// This is the fix for the user-mode super page references causing the +// machine to crash. +#define hw_rei_spe hw_rei + +#define vmaj 1 +#define vmin 18 +#define vms_pal 1 +#define osf_pal 2 +#define pal_type osf_pal +#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) + + +/////////////////////////// +// PALtemp register usage +/////////////////////////// + +// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage +// for these PALtemps: +// +// pt0 local scratch +// pt1 local scratch +// pt2 entUna pt_entUna +// pt3 CPU specific impure area pointer pt_impure +// pt4 memory management temp +// pt5 memory management temp +// pt6 memory management temp +// pt7 entIF pt_entIF +// pt8 intmask pt_intmask +// pt9 entSys pt_entSys +// pt10 +// pt11 entInt pt_entInt +// pt12 entArith pt_entArith +// pt13 reserved for system specific PAL +// pt14 reserved for system specific PAL +// pt15 reserved for system specific PAL +// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, +// pt_mces +// pt17 sysval pt_sysval +// pt18 usp pt_usp +// pt19 ksp pt_ksp +// pt20 PTBR pt_ptbr +// pt21 entMM pt_entMM +// pt22 kgp pt_kgp +// pt23 PCBB pt_pcbb +// +// + + +///////////////////////////// +// PALshadow register usage +///////////////////////////// + +// +// EV5 shadows R8-R14 and R25 when in PALmode and ICSR = 1. +// This maps the OSF PAL usage of R8 - R14 and R25: +// +// r8 ITBmiss/DTBmiss scratch +// r9 ITBmiss/DTBmiss scratch +// r10 ITBmiss/DTBmiss scratch +// r11 PS +// r12 local scratch +// r13 local scratch +// r14 local scratch +// r25 local scratch +// + + + +// .sbttl "PALcode configuration options" + +// There are a number of options that may be assembled into this version of +// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit +// the following). The options that can be adjusted cause the resultant PALcode +// to reflect the desired target system. + +// multiprocessor support can be enabled for a max of n processors by +// setting the following to the number of processors on the system. +// Note that this is really the max cpuid. + +#define max_cpuid 1 +#ifndef max_cpuid +#define max_cpuid 8 +#endif + +#define osf_svmin 1 +#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) + +// +// RESET - Reset Trap Entry Point +// +// RESET - offset 0000 +// Entry: +// Vectored into via hardware trap on reset, or branched to +// on swppal. +// +// r0 = whami +// r1 = pal_base +// r2 = base of scratch area +// r3 = halt code +// +// +// Function: +// +// + + .text 0 + . = 0x0000 + .globl _start + .globl Pal_Base +_start: +Pal_Base: + HDW_VECTOR(PAL_RESET_ENTRY) +Trap_Reset: + nop + /* + * store into r1 + */ + br r1,sys_reset + + // Specify PAL version info as a constant + // at a known location (reset + 8). + + .long osfpal_version_l // ! ! + .long osfpal_version_h // ! + .long 0 + .long 0 +pal_impure_start: + .quad 0 +pal_debug_ptr: + .quad 0 // reserved for debug pointer ; 20 + + +// +// IACCVIO - Istream Access Violation Trap Entry Point +// +// IACCVIO - offset 0080 +// Entry: +// Vectored into via hardware trap on Istream access violation or sign check error on PC. +// +// Function: +// Build stack frame +// a0 <- Faulting VA +// a1 <- MMCSR (1 for ACV) +// a2 <- -1 (for ifetch fault) +// vector via entMM +// + + HDW_VECTOR(PAL_IACCVIO_ENTRY) +Trap_Iaccvio: + DEBUGSTORE(0x42) + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS + bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_IACCVIO_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r16, osfsf_a0(sp) // save regs + bic r14, 3, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + or r31, mmcsr_c_acv, r17 // pass mm_csr as a1 + + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entmm // get entry point + + stq r11, osfsf_ps(sp) // save old ps + bis r12, r31, r11 // update ps + + stq r16, osfsf_pc(sp) // save pc + stq r29, osfsf_gp(sp) // save gp + + mtpr r13, exc_addr // load exc_addr with entMM + // 1 cycle to hw_rei + mfpr r29, pt_kgp // get the kgp + + subq r31, 1, r18 // pass flag of istream, as a2 + hw_rei_spe + + +// +// INTERRUPT - Interrupt Trap Entry Point +// +// INTERRUPT - offset 0100 +// Entry: +// Vectored into via trap on hardware interrupt +// +// Function: +// check for halt interrupt +// check for passive release (current ipl geq requestor) +// if necessary, switch to kernel mode push stack frame, +// update ps (including current mode and ipl copies), sp, and gp +// pass the interrupt info to the system module +// +// + HDW_VECTOR(PAL_INTERRUPT_ENTRY) +Trap_Interrupt: + mfpr r13, ev5__intid // Fetch level of interruptor + mfpr r25, ev5__isr // Fetch interrupt summary register + + srl r25, isr_v_hlt, r9 // Get HLT bit + mfpr r14, ev5__ipl + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern + blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set + + cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl + bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl + + and r11, osfps_m_mode, r10 // get mode bit + beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel + + mtpr r30, pt_usp // save user stack + mfpr r30, pt_ksp // get kern stack + +TRAP_INTERRUPT_10_: + lda sp, (0-osfsf_c_size)(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r11, osfsf_ps(sp) // save ps + stq r14, osfsf_pc(sp) // save pc + + stq r29, osfsf_gp(sp) // push gp + stq r16, osfsf_a0(sp) // a0 + +// pvc_violate 354 // ps is cleared anyway, if store to stack faults. + mtpr r31, ev5__ps // Set Ibox current mode to kernel + stq r17, osfsf_a1(sp) // a1 + + stq r18, osfsf_a2(sp) // a2 + subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL + + srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7. + subq r13, 0x1d, r9 // Check for 1d, 1e, 1f + + cmovge r9, r8, r12 // if .ge. 1d, then take shifted value + bis r12, r31, r11 // set new ps + + mfpr r12, pt_intmask + and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) + + /* + * Lance had space problems. We don't. + */ + extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL + mfpr r29, pt_kgp // update gp + mtpr r14, ev5__ipl // load the new IPL into Ibox + br r31, sys_interrupt // Go handle interrupt + + + +// +// ITBMISS - Istream TBmiss Trap Entry Point +// +// ITBMISS - offset 0180 +// Entry: +// Vectored into via hardware trap on Istream translation buffer miss. +// +// Function: +// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. +// Can trap into DTBMISS_DOUBLE. +// This routine can use the PALshadow registers r8, r9, and r10 +// +// + + HDW_VECTOR(PAL_ITB_MISS_ENTRY) +Trap_Itbmiss: + // Real MM mapping + nop + mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. + + nop + mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. + +pal_itb_ldq: + ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss + mtpr r10, exc_addr // Restore exc_address if there was a trap. + + mfpr r31, ev5__va // Unlock VA in case there was a double miss + nop + + and r8, osfpte_m_foe, r25 // Look for FOE set. + blbc r8, invalid_ipte_handler // PTE not valid. + + nop + bne r25, foe_ipte_handler // FOE is set + + nop + mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. + + hw_rei_stall // + + +// +// DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point +// +// DTBMISS_SINGLE - offset 0200 +// Entry: +// Vectored into via hardware trap on Dstream single translation +// buffer miss. +// +// Function: +// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. +// Can trap into DTBMISS_DOUBLE. +// This routine can use the PALshadow registers r8, r9, and r10 +// + + HDW_VECTOR(PAL_DTB_MISS_ENTRY) +Trap_Dtbmiss_Single: + mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. + mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. + +// DEBUGSTORE(0x45) +// DEBUG_EXC_ADDR() + // Real MM mapping + mfpr r9, ev5__mm_stat // Get read/write bit. E0. + mtpr r10, pt6 // Stash exc_addr away + +pal_dtb_ldq: + ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss + nop // Pad MF VA + + mfpr r10, ev5__va // Get original faulting VA for TB load. E0. + nop + + mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0. + blbc r8, invalid_dpte_handler // Handle invalid PTE + + mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. + mfpr r10, pt6 + + // Following 2 instructions take 2 cycles + mtpr r10, exc_addr // Return linkage in case we trapped. E1. + mfpr r31, pt0 // Pad the write to dtb_tag + + hw_rei // Done, return + + +// +// DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point +// +// +// DTBMISS_DOUBLE - offset 0280 +// Entry: +// Vectored into via hardware trap on Double TBmiss from single +// miss flows. +// +// r8 - faulting VA +// r9 - original MMstat +// r10 - original exc_addr (both itb,dtb miss) +// pt6 - original exc_addr (dtb miss flow only) +// VA IPR - locked with original faulting VA +// +// Function: +// Get PTE, if valid load TB and return. +// If not valid then take TNV/ACV exception. +// +// pt4 and pt5 are reserved for this flow. +// +// +// + + HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) +Trap_Dtbmiss_double: + mtpr r8, pt4 // save r8 to do exc_addr check + mfpr r8, exc_addr + blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! + mfpr r8, pt4 // restore r8 + nop + mtpr r22, pt5 // Get some scratch space. E1. + // Due to virtual scheme, we can skip the first lookup and go + // right to fetch of level 2 PTE + sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA + mtpr r21, pt4 // Get some scratch space. E1. + + srl r22, 61-page_seg_size_bits, r22 // Get Va*8 + mfpr r21, pt_ptbr // Get physical address of the page table. + + nop + addq r21, r22, r21 // Index into page table for level 2 PTE. + + sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA + ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) + + srl r22, 61-page_seg_size_bits, r22 // Get Va*8 + blbc r21, double_pte_inv // Check for Invalid PTE. + + srl r21, 32, r21 // extract PFN from PTE + sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to *8 + + addq r21, r22, r21 // Index into page table for level 3 PTE. + nop + + ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) + blbc r21, double_pte_inv // Check for invalid PTE. + + mtpr r21, ev5__dtb_pte // Write the PTE. E0. + mfpr r22, pt5 // Restore scratch register + + mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. + mfpr r21, pt4 // Restore scratch register + + nop // Pad write to tag. + nop + + nop // Pad write to tag. + nop + + hw_rei + + + +// +// UNALIGN -- Dstream unalign trap +// +// UNALIGN - offset 0300 +// Entry: +// Vectored into via hardware trap on unaligned Dstream reference. +// +// Function: +// Build stack frame +// a0 <- Faulting VA +// a1 <- Opcode +// a2 <- src/dst register number +// vector via entUna +// + + HDW_VECTOR(PAL_UNALIGN_ENTRY) +Trap_Unalign: +/* DEBUGSTORE(0x47)*/ + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss + mfpr r14, exc_addr // get pc + + srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits + blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL + + blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m + // not set, must be a load + and r13, 0x1F, r8 // isolate ra + + cmpeq r8, 0x1F, r8 // check for r31/F31 + bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault + +UNALIGN_NO_DISMISS: + bis r11, r31, r12 // Save PS + bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +UNALIGN_NO_DISMISS_10_: + mfpr r25, ev5__va // Unlock VA + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + mtpr r25, pt0 // Stash VA + stq r18, osfsf_a2(sp) // a2 + + stq r11, osfsf_ps(sp) // save old ps + srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode + + stq r29, osfsf_gp(sp) // save gp + addq r14, 4, r14 // inc PC past the ld/st + + stq r17, osfsf_a1(sp) // a1 + and r25, mm_stat_m_opcode, r17// Clean opocde for a1 + + stq r16, osfsf_a0(sp) // save regs + mfpr r16, pt0 // a0 <- va/unlock + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entuna // get entry point + + + bis r12, r31, r11 // update ps + br r31, unalign_trap_cont + + +// +// DFAULT - Dstream Fault Trap Entry Point +// +// DFAULT - offset 0380 +// Entry: +// Vectored into via hardware trap on dstream fault or sign check +// error on DVA. +// +// Function: +// Ignore faults on FETCH/FETCH_M +// Check for DFAULT in PAL +// Build stack frame +// a0 <- Faulting VA +// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) +// a2 <- R/W +// vector via entMM +// +// + HDW_VECTOR(PAL_D_FAULT_ENTRY) +Trap_Dfault: +// DEBUGSTORE(0x48) + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r13, ev5__mm_stat // Get mmstat + mfpr r8, exc_addr // get pc, preserve r14 + + srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits + blbs r8, dfault_in_pal + + bis r8, r31, r14 // move exc_addr to correct place + bis r11, r31, r12 // Save PS + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + and r9, mm_stat_m_opcode, r9 // Clean all but opcode + + cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm? + bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault + + //dismiss exception if load to r31/f31 + blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm + + // not a store or fetch, must be a load + srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits + + and r9, 0x1F, r9 // isolate rnum + nop + + cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31? + bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault + +dfault_no_dismiss: + and r13, 0xf, r13 // Clean extra bits in mm_stat + bge r25, dfault_trap_cont // no stack swap needed if cm=kern + + + mtpr r30, pt_usp // save user stack + bis r31, r31, r12 // Set new PS + + mfpr r30, pt_ksp + br r31, dfault_trap_cont + + +// +// MCHK - Machine Check Trap Entry Point +// +// MCHK - offset 0400 +// Entry: +// Vectored into via hardware trap on machine check. +// +// Function: +// +// + + HDW_VECTOR(PAL_MCHK_ENTRY) +Trap_Mchk: + DEBUGSTORE(0x49) + mtpr r31, ic_flush_ctl // Flush the Icache + br r31, sys_machine_check + + +// +// OPCDEC - Illegal Opcode Trap Entry Point +// +// OPCDEC - offset 0480 +// Entry: +// Vectored into via hardware trap on illegal opcode. +// +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + + HDW_VECTOR(PAL_OPCDEC_ENTRY) +Trap_Opcdec: + DEBUGSTORE(0x4a) +//simos DEBUG_EXC_ADDR() + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + blbs r14, pal_pal_bug_check // check opcdec in palmode + + bis r11, r31, r12 // Save PS + bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_OPCDEC_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + addq r14, 4, r14 // inc pc + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_opdec, r16 // set a0 + + stq r11, osfsf_ps(sp) // save old ps + mfpr r13, pt_entif // get entry point + + stq r18, osfsf_a2(sp) // a2 + stq r17, osfsf_a1(sp) // a1 + + stq r29, osfsf_gp(sp) // save gp + stq r14, osfsf_pc(sp) // save pc + + bis r12, r31, r11 // update ps + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei, E1 + + mfpr r29, pt_kgp // get the kgp, E1 + + hw_rei_spe // done, E1 + + +// +// ARITH - Arithmetic Exception Trap Entry Point +// +// ARITH - offset 0500 +// Entry: +// Vectored into via hardware trap on arithmetic excpetion. +// +// Function: +// Build stack frame +// a0 <- exc_sum +// a1 <- exc_mask +// a2 <- unpred +// vector via entArith +// +// + HDW_VECTOR(PAL_ARITH_ENTRY) +Trap_Arith: + DEBUGSTORE(0x4b) + and r11, osfps_m_mode, r12 // get mode bit + mfpr r31, ev5__va // unlock mbox + + bis r11, r31, r25 // save ps + mfpr r14, exc_addr // get pc + + nop + blbs r14, pal_pal_bug_check // arith trap from PAL + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + beq r12, TRAP_ARITH_10_ // if zero we are in kern now + + bis r31, r31, r25 // set the new ps + mtpr r30, pt_usp // save user stack + + nop + mfpr r30, pt_ksp // get kern stack + +TRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + nop // Pad current mode write and stq + mfpr r13, ev5__exc_sum // get the exc_sum + + mfpr r12, pt_entarith + stq r14, osfsf_pc(sp) // save pc + + stq r17, osfsf_a1(sp) + mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle + + stq r11, osfsf_ps(sp) // save ps + bis r25, r31, r11 // set new ps + + stq r16, osfsf_a0(sp) // save regs + srl r13, exc_sum_v_swc, r16 // shift data to correct position + + stq r18, osfsf_a2(sp) +// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow + mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask + + stq r29, osfsf_gp(sp) + mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 + + mfpr r29, pt_kgp // get the kern gp - E1 + hw_rei_spe // done - E1 + + +// +// FEN - Illegal Floating Point Operation Trap Entry Point +// +// FEN - offset 0580 +// Entry: +// Vectored into via hardware trap on illegal FP op. +// +// Function: +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + + HDW_VECTOR(PAL_FEN_ENTRY) +Trap_Fen: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + blbs r14, pal_pal_bug_check // check opcdec in palmode + + mfpr r13, ev5__icsr + nop + + bis r11, r31, r12 // Save PS + bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_FEN_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0 + + + stq r16, osfsf_a0(sp) // save regs + mfpr r13, pt_entif // get entry point + + stq r18, osfsf_a2(sp) // a2 + stq r11, osfsf_ps(sp) // save old ps + + stq r29, osfsf_gp(sp) // save gp + bis r12, r31, r11 // set new ps + + stq r17, osfsf_a1(sp) // a1 + blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC. + + bis r31, osf_a0_fen, r16 // set a0 + stq r14, osfsf_pc(sp) // save pc + + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei -E1 + + mfpr r29, pt_kgp // get the kgp -E1 + + hw_rei_spe // done -E1 + +// FEN trap was taken, but the fault is really opcdec. + ALIGN_BRANCH +fen_to_opcdec: + addq r14, 4, r14 // save PC+4 + bis r31, osf_a0_opdec, r16 // set a0 + + stq r14, osfsf_pc(sp) // save pc + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + hw_rei_spe // done + + + +////////////////////////////////////////////////////////////////////////////// +// Misc handlers - Start area for misc code. +////////////////////////////////////////////////////////////////////////////// + +// +// dfault_trap_cont +// A dfault trap has been taken. The sp has been updated if necessary. +// Push a stack frame a vector via entMM. +// +// Current state: +// r12 - new PS +// r13 - MMstat +// VA - locked +// +// + ALIGN_BLOCK +dfault_trap_cont: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r25, ev5__va // Fetch VA/unlock + + stq r18, osfsf_a2(sp) // a2 + and r13, 1, r18 // Clean r/w bit for a2 + + stq r16, osfsf_a0(sp) // save regs + bis r25, r31, r16 // a0 <- va + + stq r17, osfsf_a1(sp) // a1 + srl r13, 1, r17 // shift fault bits to right position + + stq r11, osfsf_ps(sp) // save old ps + bis r12, r31, r11 // update ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entmm // get entry point + + stq r29, osfsf_gp(sp) // save gp + cmovlbs r17, 1, r17 // a2. acv overrides fox. + + mtpr r25, exc_addr // load exc_addr with entMM + // 1 cycle to hw_rei + mfpr r29, pt_kgp // get the kgp + + hw_rei_spe // done + +// +//unalign_trap_cont +// An unalign trap has been taken. Just need to finish up a few things. +// +// Current state: +// r25 - entUna +// r13 - shifted MMstat +// +// + ALIGN_BLOCK +unalign_trap_cont: + mtpr r25, exc_addr // load exc_addr with entUna + // 1 cycle to hw_rei + + + mfpr r29, pt_kgp // get the kgp + and r13, mm_stat_m_ra, r18 // Clean Ra for a2 + + hw_rei_spe // done + + + +// +// dfault_in_pal +// Dfault trap was taken, exc_addr points to a PAL PC. +// r9 - mmstat right justified +// r8 - exception address +// +// These are the cases: +// opcode was STQ -- from a stack builder, KSP not valid halt +// r14 - original exc_addr +// r11 - original PS +// opcode was STL_C -- rti or retsys clear lock_flag by stack write, +// KSP not valid halt +// r11 - original PS +// r14 - original exc_addr +// opcode was LDQ -- retsys or rti stack read, KSP not valid halt +// r11 - original PS +// r14 - original exc_addr +// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables +// r10 - original exc_addr +// r11 - original PS +// +// +// + ALIGN_BLOCK +dfault_in_pal: + DEBUGSTORE(0x50) + bic r8, 3, r8 // Clean PC + mfpr r9, pal_base + + mfpr r31, va // unlock VA + + // if not real_mm, should never get here from miss flows + + subq r9, r8, r8 // pal_base - offset + + lda r9, pal_itb_ldq-pal_base(r8) + nop + + beq r9, dfault_do_bugcheck + lda r9, pal_dtb_ldq-pal_base(r8) + + beq r9, dfault_do_bugcheck + +// +// KSP invalid halt case -- +ksp_inval_halt: + DEBUGSTORE(76) + bic r11, osfps_m_mode, r11 // set ps to kernel mode + mtpr r0, pt0 + + mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode + mtpr r31, ips + + mtpr r14, exc_addr // Set PC to instruction that caused trouble + bsr r0, pal_update_pcb // update the pcb + + lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt + br r31, sys_enter_console // enter the console + + ALIGN_BRANCH +dfault_do_bugcheck: + bis r10, r31, r14 // bugcheck expects exc_addr in r14 + br r31, pal_pal_bug_check + + +// +// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 +// On entry - +// r14 - exc_addr +// VA is locked +// +// + ALIGN_BLOCK +dfault_fetch_ldr31_err: + mtpr r11, ev5__dtb_cm + mtpr r11, ev5__ps // Make sure ps hasn't changed + + mfpr r31, va // unlock the mbox + addq r14, 4, r14 // inc the pc to skip the fetch + + mtpr r14, exc_addr // give ibox new PC + mfpr r31, pt0 // pad exc_addr write + + hw_rei + + + + ALIGN_BLOCK +// +// sys_from_kern +// callsys from kernel mode - OS bugcheck machine check +// +// +sys_from_kern: + mfpr r14, exc_addr // PC points to call_pal + subq r14, 4, r14 + + lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code + br r31, pal_pal_mchk + + +// Continuation of long call_pal flows +// +// wrent_tbl +// Table to write *int in paltemps. +// 4 instructions/entry +// r16 has new value +// +// + ALIGN_BLOCK +wrent_tbl: +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entint + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entarith + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entmm + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entif + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entuna + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entsys + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + ALIGN_BLOCK +// +// tbi_tbl +// Table to do tbi instructions +// 4 instructions per entry +// +tbi_tbl: + // -2 tbia +//orig pvc_jsr tbi, dest=1 + mtpr r31, ev5__dtb_ia // Flush DTB + mtpr r31, ev5__itb_ia // Flush ITB + + hw_rei_stall + + nop // Pad table + + // -1 tbiap +//orig pvc_jsr tbi, dest=1 + mtpr r31, ev5__dtb_iap // Flush DTB + mtpr r31, ev5__itb_iap // Flush ITB + + hw_rei_stall + + nop // Pad table + + + // 0 unused +//orig pvc_jsr tbi, dest=1 + hw_rei // Pad table + nop + nop + nop + + + // 1 tbisi +//orig pvc_jsr tbi, dest=1 + + nop + nop + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall + + // 2 tbisd +//orig pvc_jsr tbi, dest=1 + mtpr r17, ev5__dtb_is // Flush DTB. + nop + + nop + hw_rei_stall + + + // 3 tbis +//orig pvc_jsr tbi, dest=1 + mtpr r17, ev5__dtb_is // Flush DTB + br r31, tbi_finish + ALIGN_BRANCH +tbi_finish: + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall + + + + ALIGN_BLOCK +// +// bpt_bchk_common: +// Finish up the bpt/bchk instructions +// +bpt_bchk_common: + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entif // get entry point + + stq r12, osfsf_ps(sp) // save old ps + stq r14, osfsf_pc(sp) // save pc + + stq r29, osfsf_gp(sp) // save gp + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + + + hw_rei_spe // done + + + ALIGN_BLOCK +// +// rti_to_user +// Finish up the rti instruction +// +rti_to_user: + mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles + mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei + + mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles + mtpr r25, pt_ksp // save off incase RTI to user + + mfpr r30, pt_usp + hw_rei_spe // and back + + + ALIGN_BLOCK +// +// rti_to_kern +// Finish up the rti instruction +// +rti_to_kern: + and r12, osfps_m_ipl, r11 // clean ps + mfpr r12, pt_intmask // get int mask + + extbl r12, r11, r12 // get mask for this ipl + mtpr r25, pt_ksp // save off incase RTI to user + + mtpr r12, ev5__ipl // set the new ipl. + or r25, r31, sp // sp + +// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals + hw_rei + + ALIGN_BLOCK +// +// swpctx_cont +// Finish up the swpctx instruction +// + +swpctx_cont: + + bic r25, r24, r25 // clean icsr + sll r12, icsr_v_fpe, r12 // shift new fen to pos + + ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr + srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 + + or r25, r12, r25 // icsr with new fen + srl r23, 32, r24 // move asn to low asn pos + + and r22, 1, r22 + sll r24, itb_asn_v_asn, r12 + + sll r22, icsr_v_pmp, r22 + nop + + or r25, r22, r25 // icsr with new pme + + sll r24, dtb_asn_v_asn, r24 + + subl r23, r13, r13 // gen new cc offset + mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 + + mtpr r24, dtb_asn // Load up new ASN + mtpr r25, icsr // write the icsr + + sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. + ldq_p r25, osfpcb_q_usp(r16) // get new usp + + insll r13, 4, r13 // >> 32 +// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow + mtpr r14, pt_ptbr // load the new ptbr + + mtpr r13, cc // set new offset + ldq_p r30, osfpcb_q_ksp(r16) // get new ksp + +// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow + mtpr r25, pt_usp // save usp + +no_pm_change_10_: hw_rei_stall // back we go + + ALIGN_BLOCK +// +// swppal_cont - finish up the swppal call_pal +// + +swppal_cont: + mfpr r2, pt_misc // get misc bits + sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit + or r2, r0, r2 // set the bit + mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel) + mtpr r2, pt_misc // update the chip + + or r3, r31, r4 + mfpr r3, pt_impure // pass pointer to the impure area in r3 +//orig fix_impure_ipr r3 // adjust impure pointer for ipr read +//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1 +//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2 +//orig unfix_impure_ipr r3 // restore impure pointer + lda r3, CNS_Q_IPR(r3) + RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3); + RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3); + lda r3, -CNS_Q_IPR(r3) + + or r31, r31, r0 // set status to success +// pvc_violate 1007 + jmp r31, (r4) // and call our friend, it's her problem now + + +swppal_fail: + addq r0, 1, r0 // set unknown pal or not loaded + hw_rei // and return + + +// .sbttl "Memory management" + + ALIGN_BLOCK +// +//foe_ipte_handler +// IFOE detected on level 3 pte, sort out FOE vs ACV +// +// on entry: +// with +// R8 = pte +// R10 = pc +// +// Function +// Determine TNV vs ACV vs FOE. Build stack and dispatch +// Will not be here if TNV. +// + +foe_ipte_handler: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + nop + +foe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack + mfpr r13, pt_entmm // get entry point + + stq r16, osfsf_a0(sp) // a0 + or r14, r31, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + nop + + stq r18, osfsf_a2(sp) // a2 + lda r17, mmcsr_c_acv(r31) // assume ACV + + stq r16, osfsf_pc(sp) // save pc + cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE + + stq r12, osfsf_ps(sp) // save ps + subq r31, 1, r18 // pass flag of istream as a2 + + stq r29, osfsf_gp(sp) + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + hw_rei_spe // out to exec + + ALIGN_BLOCK +// +//invalid_ipte_handler +// TNV detected on level 3 pte, sort out TNV vs ACV +// +// on entry: +// with +// R8 = pte +// R10 = pc +// +// Function +// Determine TNV vs ACV. Build stack and dispatch. +// + +invalid_ipte_handler: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + nop + +invalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r14 // Save pc/va in case TBmiss on stack + mfpr r13, pt_entmm // get entry point + + stq r16, osfsf_a0(sp) // a0 + or r14, r31, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + nop + + stq r18, osfsf_a2(sp) // a2 + and r25, 1, r17 // Isolate kre + + stq r16, osfsf_pc(sp) // save pc + xor r17, 1, r17 // map to acv/tnv as a1 + + stq r12, osfsf_ps(sp) // save ps + subq r31, 1, r18 // pass flag of istream as a2 + + stq r29, osfsf_gp(sp) + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + hw_rei_spe // out to exec + + + + + ALIGN_BLOCK +// +//invalid_dpte_handler +// INVALID detected on level 3 pte, sort out TNV vs ACV +// +// on entry: +// with +// R10 = va +// R8 = pte +// R9 = mm_stat +// PT6 = pc +// +// Function +// Determine TNV vs ACV. Build stack and dispatch +// + + +invalid_dpte_handler: + mfpr r12, pt6 + blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode + + bis r12, r31, r14 // save PC in case of tbmiss or fault + srl r9, mm_stat_v_opcode, r25 // shift opc to <0> + + mtpr r11, pt0 // Save PS for stack write + and r25, mm_stat_m_opcode, r25 // isolate opcode + + cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M? + blbs r25, nmiss_fetch_ldr31_err // yes + + //dismiss exception if load to r31/f31 + blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm + + // not a store or fetch, must be a load + srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits + + and r25, 0x1F, r25 // isolate rnum + nop + + cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31? + bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault + +invalid_dpte_no_dismiss: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +invalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r25 // Save va in case TBmiss on stack + and r9, 1, r13 // save r/w flag + + stq r16, osfsf_a0(sp) // a0 + or r25, r31, r16 // pass va as a0 + + stq r17, osfsf_a1(sp) // a1 + or r31, mmcsr_c_acv, r17 // assume acv + + srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0> + stq r29, osfsf_gp(sp) + + stq r18, osfsf_a2(sp) // a2 + cmovlbs r13, r25, r12 // if write access move acv based on write enable + + or r13, r31, r18 // pass flag of dstream access and read vs write + mfpr r25, pt0 // get ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r13, pt_entmm // get entry point + + stq r25, osfsf_ps(sp) // save ps + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv + + hw_rei_spe // out to exec + +// +// +// We come here if we are erring on a dtb_miss, and the instr is a +// fetch, fetch_m, of load to r31/f31. +// The PC is incremented, and we return to the program. +// essentially ignoring the instruction and error. +// +// + ALIGN_BLOCK +nmiss_fetch_ldr31_err: + mfpr r12, pt6 + addq r12, 4, r12 // bump pc to pc+4 + + mtpr r12, exc_addr // and set entry point + mfpr r31, pt0 // pad exc_addr write + + hw_rei // + + ALIGN_BLOCK +// +// double_pte_inv +// We had a single tbmiss which turned into a double tbmiss which found +// an invalid PTE. Return to single miss with a fake pte, and the invalid +// single miss flow will report the error. +// +// on entry: +// r21 PTE +// r22 available +// VA IPR locked with original fault VA +// pt4 saved r21 +// pt5 saved r22 +// pt6 original exc_addr +// +// on return to tbmiss flow: +// r8 fake PTE +// +// +// +double_pte_inv: + srl r21, osfpte_v_kre, r21 // get the kre bit to <0> + mfpr r22, exc_addr // get the pc + + lda r22, 4(r22) // inc the pc + lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set + + cmovlbc r21, r31, r8 // set to all 0 for acv if pte is 0 + mtpr r22, exc_addr // set for rei + + mfpr r21, pt4 // restore regs + mfpr r22, pt5 // restore regs + + hw_rei // back to tb miss + + ALIGN_BLOCK +// +//tnv_in_pal +// The only places in pal that ld or store are the +// stack builders, rti or retsys. Any of these mean we +// need to take a ksp not valid halt. +// +// +tnv_in_pal: + + + br r31, ksp_inval_halt + + +// .sbttl "Icache flush routines" + + ALIGN_BLOCK +// +// Common Icache flush routine. +// +// +// +pal_ic_flush: + nop + mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 + nop + nop + +// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 10 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 20 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 30 + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 40 + + nop + nop + +one_cycle_and_hw_rei: + nop + nop + + hw_rei_stall + + ALIGN_BLOCK +// +//osfpal_calpal_opcdec +// Here for all opcdec CALL_PALs +// +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + +osfpal_calpal_opcdec: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + nop + + bis r11, r31, r12 // Save PS for stack write + bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +osfpal_calpal_opcdec_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + nop + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_opdec, r16 // set a0 + + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entif // get entry point + + stq r12, osfsf_ps(sp) // save old ps + stq r17, osfsf_a1(sp) // a1 + + stq r14, osfsf_pc(sp) // save pc + nop + + stq r29, osfsf_gp(sp) // save gp + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + + + hw_rei_spe // done + + + + + +// +//pal_update_pcb +// Update the PCB with the current SP, AST, and CC info +// +// r0 - return linkage +// + ALIGN_BLOCK + +pal_update_pcb: + mfpr r12, pt_pcbb // get pcbb + and r11, osfps_m_mode, r25 // get mode + beq r25, pal_update_pcb_10_ // in kern? no need to update user sp + mtpr r30, pt_usp // save user stack + stq_p r30, osfpcb_q_usp(r12) // store usp + br r31, pal_update_pcb_20_ // join common +pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp +pal_update_pcb_20_: rpcc r13 // get cyccounter + srl r13, 32, r14 // move offset + addl r13, r14, r14 // merge for new time + stl_p r14, osfpcb_l_cc(r12) // save time + +//orig pvc_jsr updpcb, bsr=1, dest=1 + ret r31, (r0) + + +// +// pal_save_state +// +// Function +// All chip state saved, all PT's, SR's FR's, IPR's +// +// +// Regs' on entry... +// +// R0 = halt code +// pt0 = r0 +// R1 = pointer to impure +// pt4 = r1 +// R3 = return addr +// pt5 = r3 +// +// register usage: +// r0 = halt_code +// r1 = addr of impure area +// r3 = return_address +// r4 = scratch +// +// + + ALIGN_BLOCK + .globl pal_save_state +pal_save_state: +// +// +// start of implementation independent save routine +// +// the impure area is larger than the addressibility of hw_ld and hw_st +// therefore, we need to play some games: The impure area +// is informally divided into the "machine independent" part and the +// "machine dependent" part. The state that will be saved in the +// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros). +// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros). +// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg +// macros will automagically adjust the offset correctly. +// + +// The distributed code is commented out and followed by corresponding SRC code. +// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0) + +//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area + lda r1, 0x200(r1) // Point to center of CPU segment +//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag + SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag +//orig store_reg1 hlt, r0, r1, ipr=1 + SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code + + mfpr r0, pt0 // get r0 back //orig +//orig store_reg1 0, r0, r1 // save r0 + SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0 + + mfpr r0, pt4 // get r1 back //orig +//orig store_reg1 1, r0, r1 // save r1 + SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1 + +//orig store_reg 2 // save r2 + SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2 + + mfpr r0, pt5 // get r3 back //orig +//orig store_reg1 3, r0, r1 // save r3 + SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3 + + // reason code has been saved + // r0 has been saved + // r1 has been saved + // r2 has been saved + // r3 has been saved + // pt0, pt4, pt5 have been lost + + // + // Get out of shadow mode + // + + mfpr r2, icsr // Get icsr + ldah r0, (1<<(icsr_v_sde-16))(r31) + bic r2, r0, r0 // ICSR with SDE clear + mtpr r0, icsr // Turn off SDE + + mfpr r31, pt0 // SDE bubble cycle 1 + mfpr r31, pt0 // SDE bubble cycle 2 + mfpr r31, pt0 // SDE bubble cycle 3 + nop + + + // save integer regs R4-r31 + SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) + SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) + SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) + SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) + SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) + SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) + SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) + SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) + SAVE_GPR(r12,CNS_Q_GPR+0x60,r1) + SAVE_GPR(r13,CNS_Q_GPR+0x68,r1) + SAVE_GPR(r14,CNS_Q_GPR+0x70,r1) + SAVE_GPR(r15,CNS_Q_GPR+0x78,r1) + SAVE_GPR(r16,CNS_Q_GPR+0x80,r1) + SAVE_GPR(r17,CNS_Q_GPR+0x88,r1) + SAVE_GPR(r18,CNS_Q_GPR+0x90,r1) + SAVE_GPR(r19,CNS_Q_GPR+0x98,r1) + SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1) + SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1) + SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1) + SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1) + SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1) + SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1) + SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1) + SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1) + SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1) + SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) + SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) + SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) + + // save all paltemp regs except pt0 + +//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores +//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores + + lda r1, -0x200(r1) // Restore the impure base address. + lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. + SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle + SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) + SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) + SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) + SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) + SAVE_IPR(pt5,CNS_Q_PT+0x28,r1) + SAVE_IPR(pt6,CNS_Q_PT+0x30,r1) + SAVE_IPR(pt7,CNS_Q_PT+0x38,r1) + SAVE_IPR(pt8,CNS_Q_PT+0x40,r1) + SAVE_IPR(pt9,CNS_Q_PT+0x48,r1) + SAVE_IPR(pt10,CNS_Q_PT+0x50,r1) + SAVE_IPR(pt11,CNS_Q_PT+0x58,r1) + SAVE_IPR(pt12,CNS_Q_PT+0x60,r1) + SAVE_IPR(pt13,CNS_Q_PT+0x68,r1) + SAVE_IPR(pt14,CNS_Q_PT+0x70,r1) + SAVE_IPR(pt15,CNS_Q_PT+0x78,r1) + SAVE_IPR(pt16,CNS_Q_PT+0x80,r1) + SAVE_IPR(pt17,CNS_Q_PT+0x88,r1) + SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) + SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) + SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) + SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) + SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) + SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) + + // Restore shadow mode + mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) + mfpr r31, pt0 + mtpr r2, icsr // Restore original ICSR + + mfpr r31, pt0 // SDE bubble cycle 1 + mfpr r31, pt0 // SDE bubble cycle 2 + mfpr r31, pt0 // SDE bubble cycle 3 + nop + + // save all integer shadow regs + SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code + SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) + SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) + SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) + SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) + SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) + SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) + SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) + + SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) + SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) + SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) + SAVE_IPR(va,CNS_Q_VA,r1) + SAVE_IPR(icsr,CNS_Q_ICSR,r1) + SAVE_IPR(ipl,CNS_Q_IPL,r1) + SAVE_IPR(ips,CNS_Q_IPS,r1) + SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) + SAVE_IPR(aster,CNS_Q_ASTER,r1) + SAVE_IPR(astrr,CNS_Q_ASTRR,r1) + SAVE_IPR(sirr,CNS_Q_SIRR,r1) + SAVE_IPR(isr,CNS_Q_ISR,r1) + SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1) + SAVE_IPR(mcsr,CNS_Q_MCSR,r1) + SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1) + +//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st) +//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for +//orig // PVC violation applies only to +pvc$osf35$379: // loads. HW_ST ok here, so ignore + SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 + + + //the following iprs are informational only -- will not be restored + + SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) + SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) + SAVE_IPR(intId,CNS_Q_INT_ID,r1) + SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) + SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) + ldah r14, 0xFFF0(zero) + zap r14, 0xE0, r14 // Get base address of CBOX IPRs + NOP // Pad mfpr dcPerr out of shadow of + NOP // last store + NOP + SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) + + // read cbox ipr state + + mb + ldq_p r2, scCtl(r14) + ldq_p r13, ldLock(r14) + ldq_p r4, scAddr(r14) + ldq_p r5, eiAddr(r14) + ldq_p r6, bcTagAddr(r14) + ldq_p r7, fillSyn(r14) + bis r5, r4, zero // Make sure all loads complete before + bis r7, r6, zero // reading registers that unlock them. + ldq_p r8, scStat(r14) // Unlocks scAddr. + ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. + ldq_p zero, eiStat(r14) // Make sure it is really unlocked. + mb + + // save cbox ipr state + SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); + SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); + SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); + SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); + SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); + SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); + SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); + SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); + //bc_config? sl_rcv? + +// restore impure base +//orig unfix_impure_ipr r1 + lda r1, -CNS_Q_IPR(r1) + +// save all floating regs + mfpr r0, icsr // get icsr + or r31, 1, r2 // get a one + sll r2, icsr_v_fpe, r2 // Shift it into ICSR position + or r2, r0, r0 // set FEN on + mtpr r0, icsr // write to icsr, enabling FEN + +// map the save area virtually + mtpr r31, dtbIa // Clear all DTB entries + srl r1, va_s_off, r0 // Clean off byte-within-page offset + sll r0, pte_v_pfn, r0 // Shift to form PFN + lda r0, pte_m_prot(r0) // Set all read/write enable bits + mtpr r0, dtbPte // Load the PTE and set valid + mtpr r1, dtbTag // Write the PTE and tag into the DTB + + +// map the next page too - in case the impure area crosses a page boundary + lda r4, (1< and ICSR + mtpr r0, icsr // Update the chip + + mfpr r31, pt0 // FPE bubble cycle 1 //orig + mfpr r31, pt0 // FPE bubble cycle 2 //orig + mfpr r31, pt0 // FPE bubble cycle 3 //orig + +//orig fix_impure_ipr r1 +//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 +//orig mt_fpcr f0 +//orig +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access + lda r1, 200(r1) // Point to base of IPR area again + RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb + mt_fpcr f0 // original + + lda r1, 0x200(r1) // point to center of CPU segment + +// restore all floating regs + RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) + RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) + RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) + RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) + RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) + RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) + RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) + RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) + RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1) + RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1) + RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1) + RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1) + RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1) + RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1) + RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1) + RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1) + RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1) + RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1) + RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1) + RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1) + RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1) + RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1) + RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1) + RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1) + RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1) + RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) + RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) + RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) + RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) + RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) + RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) + RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) + +// switch impure pointer from gpr to ipr area -- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 + lda r1, -0x200(r1) // Restore base address of impure area. + lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. + +// restore all pal regs + RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle + RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) + RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) + RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) + RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) + RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) + RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) + RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) + RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1) + RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1) + RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1) + RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1) + RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1) + RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1) + RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1) + RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1) + RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1) + RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1) + RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1) + RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1) + RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1) + RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1) + RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1) + RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1) + + +//orig restore_reg exc_addr, ipr=1 // restore ipr +//orig restore_reg pal_base, ipr=1 // restore ipr +//orig restore_reg ipl, ipr=1 // restore ipr +//orig restore_reg ps, ipr=1 // restore ipr +//orig mtpr r0, dtb_cm // set current mode in mbox too +//orig restore_reg itb_asn, ipr=1 +//orig srl r0, itb_asn_v_asn, r0 +//orig sll r0, dtb_asn_v_asn, r0 +//orig mtpr r0, dtb_asn // set ASN in Mbox too +//orig restore_reg ivptbr, ipr=1 +//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr +//orig restore_reg mcsr, ipr=1 +//orig restore_reg aster, ipr=1 +//orig restore_reg astrr, ipr=1 +//orig restore_reg sirr, ipr=1 +//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles +//orig mfpr r31, pt0 // (may issue with mt maf_mode) +//orig mfpr r31, pt0 // bubble cycle 1 +//orig mfpr r31, pt0 // bubble cycle 2 +//orig mfpr r31, pt0 // bubble cycle 3 +//orig mfpr r31, pt0 // (may issue with following ld) + + // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag) + RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) + RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1) + RESTORE_IPR(ipl,CNS_Q_IPL,r1) + RESTORE_IPR(ips,CNS_Q_IPS,r1) + mtpr r0, dtbCm // Set Mbox current mode too. + RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) + srl r0, 4, r0 + sll r0, 57, r0 + mtpr r0, dtbAsn // Set Mbox ASN too + RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1) + mtpr r0, mVptBr // Set Mbox VptBr too + RESTORE_IPR(mcsr,CNS_Q_MCSR,r1) + RESTORE_IPR(aster,CNS_Q_ASTER,r1) + RESTORE_IPR(astrr,CNS_Q_ASTRR,r1) + RESTORE_IPR(sirr,CNS_Q_SIRR,r1) + RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1) + STALL + STALL + STALL + STALL + STALL + + + // restore all integer shadow regs + RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code + RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) + RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) + RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) + RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) + RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) + RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) + RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) + RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) + + // + // Get out of shadow mode + // + + mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) + mfpr r31, pt0 // "" + mfpr r0, icsr // Get icsr + ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location + bic r0, r2, r2 // ICSR with SDE clear + mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles + + mfpr r31, pt0 // SDE bubble cycle 1 + mfpr r31, pt0 // SDE bubble cycle 2 + mfpr r31, pt0 // SDE bubble cycle 3 + nop + +// switch impure pointer from ipr to gpr area -- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 + +// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... + + lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area + lda r1, 0x200(r1) // Point to center of CPU segment + + // restore all integer regs + RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) + RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) + RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) + RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) + RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) + RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) + RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) + RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) + RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1) + RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1) + RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1) + RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1) + RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1) + RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1) + RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1) + RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1) + RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1) + RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1) + RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1) + RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1) + RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1) + RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1) + RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1) + RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1) + RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1) + RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1) + RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1) + RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1) + +//orig // switch impure pointer from gpr to ipr area -- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 +//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei + + lda t0, -0x200(t0) // Restore base address of impure area. + lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again. + RESTORE_IPR(icsr,CNS_Q_ICSR,r1) + +//orig // and back again -- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 +//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag +//orig mb + + lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again, + lda t0, 0x200(t0) // and back to center of CPU segment + SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag + mb + +//orig // and back we go +//orig// restore_reg 3 +//orig restore_reg 2 +//orig// restore_reg 1 +//orig restore_reg 0 +//orig // restore impure area base +//orig unfix_impure_gpr r1 + + RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) + RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) + lda r1, -0x200(r1) // Restore impure base address + + mfpr r31, pt0 // stall for ldq_p above //orig + + mtpr r31, dtb_ia // clear the tb //orig + mtpr r31, itb_ia // clear the itb //orig + +//orig pvc_jsr rststa, bsr=1, dest=1 + ret r31, (r3) // back we go //orig + + +// +// pal_pal_bug_check -- code has found a bugcheck situation. +// Set things up and join common machine check flow. +// +// Input: +// r14 - exc_addr +// +// On exit: +// pt0 - saved r0 +// pt1 - saved r1 +// pt4 - saved r4 +// pt5 - saved r5 +// pt6 - saved r6 +// pt10 - saved exc_addr +// pt_misc<47:32> - mchk code +// pt_misc<31:16> - scb vector +// r14 - base of Cbox IPRs in IO space +// MCES is set +// + + ALIGN_BLOCK + .globl pal_pal_bug_check_from_int +pal_pal_bug_check_from_int: + DEBUGSTORE(0x79) +//simos DEBUG_EXC_ADDR() + DEBUGSTORE(0x20) +//simos bsr r25, put_hex + lda r25, mchk_c_bugcheck(r31) + addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed + br r31, pal_pal_mchk + nop + +pal_pal_bug_check: + lda r25, mchk_c_bugcheck(r31) + +pal_pal_mchk: + sll r25, 32, r25 // Move mchk code to position + + mtpr r14, pt10 // Stash exc_addr + mtpr r14, exc_addr + + mfpr r12, pt_misc // Get MCES and scratch + zap r12, 0x3c, r12 + + or r12, r25, r12 // Combine mchk code + lda r25, scb_v_procmchk(r31) // Get SCB vector + + sll r25, 16, r25 // Move SCBv to position + or r12, r25, r25 // Combine SCBv + + mtpr r0, pt0 // Stash for scratch + bis r25, mces_m_mchk, r25 // Set MCES bit + + mtpr r25, pt_misc // Save mchk code!scbv!whami!mces + ldah r14, 0xfff0(r31) + + mtpr r1, pt1 // Stash for scratch + zap r14, 0xE0, r14 // Get Cbox IPR base + + mtpr r4, pt4 + mtpr r5, pt5 + + mtpr r6, pt6 + blbs r12, sys_double_machine_check // MCHK halt if double machine check + + br r31, sys_mchk_collect_iprs // Join common machine check flow + + + +// align_to_call_pal_section +// Align to address of first call_pal entry point - 2000 + +// +// HALT - PALcode for HALT instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// GO to console code +// +// + + .text 1 +// . = 0x2000 + CALL_PAL_PRIV(PAL_HALT_ENTRY) +call_pal_halt: + mfpr r31, pt0 // Pad exc_addr read + mfpr r31, pt0 + + mfpr r12, exc_addr // get PC + subq r12, 4, r12 // Point to the HALT + + mtpr r12, exc_addr + mtpr r0, pt0 + +//orig pvc_jsr updpcb, bsr=1 + bsr r0, pal_update_pcb // update the pcb + lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt + br r31, sys_enter_console // enter the console + +// +// CFLUSH - PALcode for CFLUSH instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// R16 - contains the PFN of the page to be flushed +// +// Function: +// Flush all Dstream caches of 1 entire page +// The CFLUSH routine is in the system specific module. +// +// + + CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) +Call_Pal_Cflush: + br r31, sys_cflush + +// +// DRAINA - PALcode for DRAINA instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// Implicit TRAPB performed by hardware. +// +// Function: +// Stall instruction issue until all prior instructions are guaranteed to +// complete without incurring aborts. For the EV5 implementation, this +// means waiting until all pending DREADS are returned. +// +// + + CALL_PAL_PRIV(PAL_DRAINA_ENTRY) +Call_Pal_Draina: + ldah r14, 0x100(r31) // Init counter. Value? + nop + +DRAINA_LOOP: + subq r14, 1, r14 // Decrement counter + mfpr r13, ev5__maf_mode // Fetch status bit + + srl r13, maf_mode_v_dread_pending, r13 + ble r14, DRAINA_LOOP_TOO_LONG + + nop + blbs r13, DRAINA_LOOP // Wait until all DREADS clear + + hw_rei + +DRAINA_LOOP_TOO_LONG: + br r31, call_pal_halt + +// CALL_PAL OPCDECs + + CALL_PAL_PRIV(0x0003) +CallPal_OpcDec03: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0004) +CallPal_OpcDec04: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0005) +CallPal_OpcDec05: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0006) +CallPal_OpcDec06: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0007) +CallPal_OpcDec07: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0008) +CallPal_OpcDec08: + br r31, osfpal_calpal_opcdec + +// +// CSERVE - PALcode for CSERVE instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Various functions for private use of console software +// +// option selector in r0 +// arguments in r16.... +// The CSERVE routine is in the system specific module. +// +// + + CALL_PAL_PRIV(PAL_CSERVE_ENTRY) +Call_Pal_Cserve: + br r31, sys_cserve + +// +// swppal - PALcode for swppal instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// Vectored into via hardware PALcode instruction dispatch. +// R16 contains the new PAL identifier +// R17:R21 contain implementation-specific entry parameters +// +// R0 receives status: +// 0 success (PAL was switched) +// 1 unknown PAL variant +// 2 known PAL variant, but PAL not loaded +// +// +// Function: +// Swap control to another PAL. +// + + CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) +Call_Pal_Swppal: + cmpule r16, 255, r0 // see if a kibble was passed + cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) + + or r16, r31, r3 // set r3 incase this is a address + blbc r0, swppal_cont // nope, try it as an address + + cmpeq r16, 2, r0 // is it our friend OSF? + blbc r0, swppal_fail // nope, don't know this fellow + + br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF + +// .global osfpal_hw_entry_reset +// .weak osfpal_hw_entry_reset +// .long +//orig halt // don't know how to get the address here - kludge ok, load pal at 0 + .long 0 // ?? hack upon hack...pb + +CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr +// ble r3, swppal_fail ; if OSF not linked in say not loaded. + mfpr r2, pal_base // fetch pal base + + addq r2, r3, r3 // add pal base + lda r2, 0x3FFF(r31) // get pal base checker mask + + and r3, r2, r2 // any funky bits set? + cmpeq r2, 0, r0 // + + blbc r0, swppal_fail // return unknown if bad bit set. + br r31, swppal_cont + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x000B) +CallPal_OpcDec0B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x000C) +CallPal_OpcDec0C: + br r31, osfpal_calpal_opcdec + +// +// wripir - PALcode for wripir instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// r16 = processor number to interrupt +// +// Function: +// IPIR <- R16 +// Handled in system-specific code +// +// Exit: +// interprocessor interrupt is recorded on the target processor +// and is initiated when the proper enabling conditions are present. +// + + CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) +Call_Pal_Wrpir: + br r31, sys_wripir + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x000E) +CallPal_OpcDec0E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x000F) +CallPal_OpcDec0F: + br r31, osfpal_calpal_opcdec + +// +// rdmces - PALcode for rdmces instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// R0 <- ZEXT(MCES) +// + + CALL_PAL_PRIV(PAL_RDMCES_ENTRY) +Call_Pal_Rdmces: + mfpr r0, pt_mces // Read from PALtemp + and r0, mces_m_all, r0 // Clear other bits + + hw_rei + +// +// wrmces - PALcode for wrmces instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) +// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) +// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) +// MCES<3> <- R16<3> (DPC) +// MCES<4> <- R16<4> (DSC) +// +// + + CALL_PAL_PRIV(PAL_WRMCES_ENTRY) +Call_Pal_Wrmces: + and r16, ((1<read restriction + + nop + hw_rei + + + +// CALL_PAL OPCDECs + + CALL_PAL_PRIV(0x0012) +CallPal_OpcDec12: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0013) +CallPal_OpcDec13: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0014) +CallPal_OpcDec14: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0015) +CallPal_OpcDec15: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0016) +CallPal_OpcDec16: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0017) +CallPal_OpcDec17: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0018) +CallPal_OpcDec18: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0019) +CallPal_OpcDec19: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001A) +CallPal_OpcDec1A: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001B) +CallPal_OpcDec1B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001C) +CallPal_OpcDec1C: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001D) +CallPal_OpcDec1D: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001E) +CallPal_OpcDec1E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001F) +CallPal_OpcDec1F: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0020) +CallPal_OpcDec20: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0021) +CallPal_OpcDec21: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0022) +CallPal_OpcDec22: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0023) +CallPal_OpcDec23: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0024) +CallPal_OpcDec24: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0025) +CallPal_OpcDec25: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0026) +CallPal_OpcDec26: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0027) +CallPal_OpcDec27: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0028) +CallPal_OpcDec28: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0029) +CallPal_OpcDec29: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x002A) +CallPal_OpcDec2A: + br r31, osfpal_calpal_opcdec + +// +// wrfen - PALcode for wrfen instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// a0<0> -> ICSR +// Store new FEN in PCB +// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) +// are UNPREDICTABLE +// +// Issue: What about pending FP loads when FEN goes from on->off???? +// + + CALL_PAL_PRIV(PAL_WRFEN_ENTRY) +Call_Pal_Wrfen: + or r31, 1, r13 // Get a one + mfpr r1, ev5__icsr // Get current FPE + + sll r13, icsr_v_fpe, r13 // shift 1 to icsr spot, e0 + and r16, 1, r16 // clean new fen + + sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position + bic r1, r13, r1 // zero icsr + + or r1, r12, r1 // Or new FEN into ICSR + mfpr r12, pt_pcbb // Get PCBB - E1 + + mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI + stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB. + + mfpr r31, pt0 // Pad ICSR write. + mfpr r31, pt0 + + mfpr r31, pt0 +// pvc_violate 225 // cuz PVC can't distinguish which bits changed + hw_rei + + + CALL_PAL_PRIV(0x002C) +CallPal_OpcDec2C: + br r31, osfpal_calpal_opcdec + +// +// wrvptpr - PALcode for wrvptpr instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// vptptr <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) +Call_Pal_Wrvptptr: + mtpr r16, ev5__mvptbr // Load Mbox copy + mtpr r16, ev5__ivptbr // Load Ibox copy + nop // Pad IPR write + nop + hw_rei + + CALL_PAL_PRIV(0x002E) +CallPal_OpcDec2E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x002F) +CallPal_OpcDec2F: + br r31, osfpal_calpal_opcdec + + +// +// swpctx - PALcode for swpctx instruction +// +// Entry: +// hardware dispatch via callPal instruction +// R16 -> new pcb +// +// Function: +// dynamic state moved to old pcb +// new state loaded from new pcb +// pcbb pointer set +// old pcbb returned in R0 +// +// Note: need to add perf monitor stuff +// + + CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) +Call_Pal_Swpctx: + rpcc r13 // get cyccounter + mfpr r0, pt_pcbb // get pcbb + + ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme + ldq_p r23, osfpcb_l_cc(r16) // get new asn + + srl r13, 32, r25 // move offset + mfpr r24, pt_usp // get usp + + stq_p r30, osfpcb_q_ksp(r0) // store old ksp +// pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow. + mtpr r16, pt_pcbb // set new pcbb + + stq_p r24, osfpcb_q_usp(r0) // store usp + addl r13, r25, r25 // merge for new time + + stl_p r25, osfpcb_l_cc(r0) // save time + ldah r24, (1<<(icsr_v_fpe-16))(r31) + + and r22, 1, r12 // isolate fen + mfpr r25, icsr // get current icsr + + lda r24, (1< +// PS <- a0<2:0> (r16) +// +// t8 (r22) is scratch +// + + CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) +Call_Pal_Swpipl: + and r16, osfps_m_ipl, r16 // clean New ipl + mfpr r22, pt_intmask // get int mask + + extbl r22, r16, r22 // get mask for this ipl + bis r11, r31, r0 // return old ipl + + bis r16, r31, r11 // set new ps + mtpr r22, ev5__ipl // set new mask + + mfpr r31, pt0 // pad ipl write + mfpr r31, pt0 // pad ipl write + + hw_rei // back + +// +// rdps - PALcode for rdps instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- ps +// + + CALL_PAL_PRIV(PAL_RDPS_ENTRY) +Call_Pal_Rdps: + bis r11, r31, r0 // Fetch PALshadow PS + nop // Must be 2 cycles long + hw_rei + +// +// wrkgp - PALcode for wrkgp instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// kgp <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRKGP_ENTRY) +Call_Pal_Wrkgp: + nop + mtpr r16, pt_kgp + nop // Pad for pt write->read restriction + nop + hw_rei + +// +// wrusp - PALcode for wrusp instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// usp <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRUSP_ENTRY) +Call_Pal_Wrusp: + nop + mtpr r16, pt_usp + nop // Pad possible pt write->read restriction + nop + hw_rei + +// +// wrperfmon - PALcode for wrperfmon instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// +// Function: +// Various control functions for the onchip performance counters +// +// option selector in r16 +// option argument in r17 +// returned status in r0 +// +// +// r16 = 0 Disable performance monitoring for one or more cpu's +// r17 = 0 disable no counters +// r17 = bitmask disable counters specified in bit mask (1=disable) +// +// r16 = 1 Enable performance monitoring for one or more cpu's +// r17 = 0 enable no counters +// r17 = bitmask enable counters specified in bit mask (1=enable) +// +// r16 = 2 Mux select for one or more cpu's +// r17 = Mux selection (cpu specific) +// <24:19> bc_ctl field (see spec) +// <31>,<7:4>,<3:0> pmctr ,, fields (see spec) +// +// r16 = 3 Options +// r17 = (cpu specific) +// <0> = 0 log all processes +// <0> = 1 log only selected processes +// <30,9,8> mode select - ku,kp,kk +// +// r16 = 4 Interrupt frequency select +// r17 = (cpu specific) indicates interrupt frequencies desired for each +// counter, with "zero interrupts" being an option +// frequency info in r17 bits as defined by PMCTR_CTL below +// +// r16 = 5 Read Counters +// r17 = na +// r0 = value (same format as ev5 pmctr) +// <0> = 0 Read failed +// <0> = 1 Read succeeded +// +// r16 = 6 Write Counters +// r17 = value (same format as ev5 pmctr; all counters written simultaneously) +// +// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0 +// r17 = 0 enable no counters +// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear) +// +//============================================================================= +//Assumptions: +//PMCTR_CTL: +// +// <15:14> CTL0 -- encoded frequency select and enable - CTR0 +// <13:12> CTL1 -- " - CTR1 +// <11:10> CTL2 -- " - CTR2 +// +// <9:8> FRQ0 -- frequency select for CTR0 (no enable info) +// <7:6> FRQ1 -- frequency select for CTR1 +// <5:4> FRQ2 -- frequency select for CTR2 +// +// <0> all vs. select processes (0=all,1=select) +// +// where +// FRQx<1:0> +// 0 1 disable interrupt +// 1 0 frequency = 65536 (16384 for ctr2) +// 1 1 frequency = 256 +// note: FRQx<1:0> = 00 will keep counters from ever being enabled. +// +//============================================================================= +// + CALL_PAL_PRIV(0x0039) +// unsupported in Hudson code .. pboyle Nov/95 +CALL_PAL_Wrperfmon: + // "real" performance monitoring code + cmpeq r16, 1, r0 // check for enable + bne r0, perfmon_en // br if requested to enable + + cmpeq r16, 2, r0 // check for mux ctl + bne r0, perfmon_muxctl // br if request to set mux controls + + cmpeq r16, 3, r0 // check for options + bne r0, perfmon_ctl // br if request to set options + + cmpeq r16, 4, r0 // check for interrupt frequency select + bne r0, perfmon_freq // br if request to change frequency select + + cmpeq r16, 5, r0 // check for counter read request + bne r0, perfmon_rd // br if request to read counters + + cmpeq r16, 6, r0 // check for counter write request + bne r0, perfmon_wr // br if request to write counters + + cmpeq r16, 7, r0 // check for counter clear/enable request + bne r0, perfmon_enclr // br if request to clear/enable counters + + beq r16, perfmon_dis // br if requested to disable (r16=0) + br r31, perfmon_unknown // br if unknown request + +// +// rdusp - PALcode for rdusp instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- usp +// + + CALL_PAL_PRIV(PAL_RDUSP_ENTRY) +Call_Pal_Rdusp: + nop + mfpr r0, pt_usp + hw_rei + + + CALL_PAL_PRIV(0x003B) +CallPal_OpcDec3B: + br r31, osfpal_calpal_opcdec + +// +// whami - PALcode for whami instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- whami +// + CALL_PAL_PRIV(PAL_WHAMI_ENTRY) +Call_Pal_Whami: + nop + mfpr r0, pt_whami // Get Whami + extbl r0, 1, r0 // Isolate just whami bits + hw_rei + +// +// retsys - PALcode for retsys instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// 00(sp) contains return pc +// 08(sp) contains r29 +// +// Function: +// Return from system call. +// mode switched from kern to user. +// stacks swapped, ugp, upc restored. +// r23, r25 junked +// + + CALL_PAL_PRIV(PAL_RETSYS_ENTRY) +Call_Pal_Retsys: + lda r25, osfsf_c_size(sp) // pop stack + bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr + + mfpr r14, exc_addr // save exc_addr in case of fault + ldq r23, osfsf_pc(sp) // get pc + + ldq r29, osfsf_gp(sp) // get gp + stl_c r31, -4(sp) // clear lock_flag + + lda r11, 1<