dev, arm: Refactor and clean up the generic timer model
This changeset cleans up the generic timer a bit and moves most of the register juggling from the ISA code into a separate class in the same source file as the rest of the generic timer. It also removes the assumption that there is always 8 or fewer CPUs in the system. Instead of having a fixed limit, we now instantiate per-core timers as they are requested. This is all in preparation for other patches that add support for virtual timers and a memory mapped interface.
This commit is contained in:
Andreas Sandberg
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013 ARM Limited
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* Copyright (c) 2013, 2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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@@ -35,13 +35,15 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Giacomo Gabrielli
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* Andreas Sandberg
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*/
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#ifndef __DEV_ARM_GENERIC_TIMER_HH__
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#define __DEV_ARM_GENERIC_TIMER_HH__
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#include "arch/arm/isa_device.hh"
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#include "base/bitunion.hh"
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#include "params/GenericTimer.hh"
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#include "dev/arm/base_gic.hh"
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#include "sim/core.hh"
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#include "sim/sim_object.hh"
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@@ -51,149 +53,209 @@
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/// ARM, Issue C, Chapter 17).
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class Checkpoint;
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class BaseGic;
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class GenericTimerParams;
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/// Wrapper around the actual counters and timers of the Generic Timer
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/// extension.
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class GenericTimer : public SimObject
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/// Global system counter. It is shared by the architected timers.
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/// @todo: implement memory-mapped controls
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class SystemCounter
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{
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protected:
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/// Counter frequency (as specified by CNTFRQ).
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uint64_t _freq;
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/// Cached copy of the counter period (inverse of the frequency).
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Tick _period;
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/// Tick when the counter was reset.
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Tick _resetTick;
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uint32_t _regCntkctl;
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public:
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SystemCounter();
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/// Returns the current value of the physical counter.
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uint64_t value() const
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{
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if (_freq == 0)
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return 0; // Counter is still off.
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return (curTick() - _resetTick) / _period;
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}
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/// Returns the counter frequency.
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uint64_t freq() const { return _freq; }
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/// Sets the counter frequency.
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/// @param freq frequency in Hz.
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void setFreq(uint32_t freq);
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/// Returns the counter period.
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Tick period() const { return _period; }
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void setKernelControl(uint32_t val) { _regCntkctl = val; }
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uint32_t getKernelControl() { return _regCntkctl; }
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void serialize(std::ostream &os) const;
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void unserialize(Checkpoint *cp, const std::string §ion);
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private:
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// Disable copying
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SystemCounter(const SystemCounter &c);
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};
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/// Per-CPU architected timer.
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class ArchTimer
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{
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public:
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/// Global system counter. It is shared by the architected timers.
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/// @todo: implement memory-mapped controls
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class SystemCounter
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class Interrupt
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{
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protected:
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/// Counter frequency (as specified by CNTFRQ).
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uint64_t _freq;
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/// Cached copy of the counter period (inverse of the frequency).
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Tick _period;
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/// Tick when the counter was reset.
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Tick _resetTick;
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public:
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/// Ctor.
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SystemCounter()
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: _freq(0), _period(0), _resetTick(0)
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{
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setFreq(0x01800000);
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}
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Interrupt(BaseGic &gic, unsigned irq)
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: _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
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/// Returns the current value of the physical counter.
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uint64_t value() const
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{
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if (_freq == 0)
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return 0; // Counter is still off.
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return (curTick() - _resetTick) / _period;
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}
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Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
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: _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
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/// Returns the counter frequency.
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uint64_t freq() const { return _freq; }
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/// Sets the counter frequency.
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/// @param freq frequency in Hz.
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void setFreq(uint32_t freq);
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void send();
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void clear();
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/// Returns the counter period.
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Tick period() const { return _period; }
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/// Per-CPU architected timer.
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class ArchTimer
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{
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protected:
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/// Control register.
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BitUnion32(ArchTimerCtrl)
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Bitfield<0> enable;
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Bitfield<1> imask;
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Bitfield<2> istatus;
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EndBitUnion(ArchTimerCtrl)
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/// Name of this timer.
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std::string _name;
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/// Pointer to parent class.
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GenericTimer *_parent;
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/// Pointer to the global system counter.
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SystemCounter *_counter;
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/// ID of the CPU this timer is attached to.
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int _cpuNum;
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/// ID of the interrupt to be triggered.
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int _intNum;
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/// Cached value of the control register ({CNTP/CNTHP/CNTV}_CTL).
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ArchTimerCtrl _control;
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/// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
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uint64_t _counterLimit;
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/// Called when the upcounter reaches the programmed value.
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void counterLimitReached();
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EventWrapper<ArchTimer, &ArchTimer::counterLimitReached>
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_counterLimitReachedEvent;
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/// Returns the value of the counter which this timer relies on.
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uint64_t counterValue() const { return _counter->value(); }
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public:
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/// Ctor.
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ArchTimer()
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: _control(0), _counterLimit(0), _counterLimitReachedEvent(this)
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{}
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/// Returns the timer name.
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std::string name() const { return _name; }
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/// Returns the CompareValue view of the timer.
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uint64_t compareValue() const { return _counterLimit; }
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/// Sets the CompareValue view of the timer.
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void setCompareValue(uint64_t val);
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/// Returns the TimerValue view of the timer.
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uint32_t timerValue() const { return _counterLimit - counterValue(); }
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/// Sets the TimerValue view of the timer.
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void setTimerValue(uint32_t val);
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/// Sets the control register.
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uint32_t control() const { return _control; }
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void setControl(uint32_t val);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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friend class GenericTimer;
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private:
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BaseGic &_gic;
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const bool _ppi;
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const unsigned _irq;
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const unsigned _cpu;
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};
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protected:
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/// Control register.
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BitUnion32(ArchTimerCtrl)
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Bitfield<0> enable;
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Bitfield<1> imask;
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Bitfield<2> istatus;
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EndBitUnion(ArchTimerCtrl)
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static const int CPU_MAX = 8;
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/// Name of this timer.
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const std::string _name;
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/// Pointer to the GIC, needed to trigger timer interrupts.
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BaseGic *_gic;
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/// System counter.
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SystemCounter _systemCounter;
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/// Per-CPU architected timers.
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// @todo: this would become a 2-dim. array with Security and Virt.
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ArchTimer _archTimers[CPU_MAX];
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/// Pointer to parent class.
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SimObject &_parent;
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SystemCounter &_systemCounter;
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Interrupt _interrupt;
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/// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
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ArchTimerCtrl _control;
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/// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
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uint64_t _counterLimit;
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/**
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* Timer settings or the offset has changed, re-evaluate
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* trigger condition and raise interrupt if necessary.
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*/
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void updateCounter();
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/// Called when the upcounter reaches the programmed value.
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void counterLimitReached();
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EventWrapper<ArchTimer, &ArchTimer::counterLimitReached>
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_counterLimitReachedEvent;
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public:
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typedef GenericTimerParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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ArchTimer(const std::string &name,
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SimObject &parent,
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SystemCounter &sysctr,
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const Interrupt &interrupt);
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/// Returns the timer name.
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std::string name() const { return _name; }
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/// Returns the CompareValue view of the timer.
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uint64_t compareValue() const { return _counterLimit; }
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/// Sets the CompareValue view of the timer.
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void setCompareValue(uint64_t val);
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/// Returns the TimerValue view of the timer.
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uint32_t timerValue() const { return _counterLimit - value(); }
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/// Sets the TimerValue view of the timer.
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void setTimerValue(uint32_t val);
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/// Sets the control register.
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uint32_t control() const { return _control; }
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void setControl(uint32_t val);
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/// Returns the value of the counter which this timer relies on.
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uint64_t value() const;
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void serialize(std::ostream &os) const;
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void unserialize(Checkpoint *cp, const std::string §ion);
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private:
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// Disable copying
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ArchTimer(const ArchTimer &t);
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};
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class GenericTimer : public SimObject
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{
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public:
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GenericTimer(GenericTimerParams *p);
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void serialize(std::ostream &os) M5_ATTR_OVERRIDE;
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void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
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public:
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void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
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ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
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protected:
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struct CoreTimers {
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CoreTimers(GenericTimer &parent, unsigned cpu,
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unsigned _irqPhys)
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: irqPhys(*parent.gic, _irqPhys, cpu),
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// This should really be phys_timerN, but we are stuck with
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// arch_timer for backwards compatibility.
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phys(csprintf("%s.arch_timer%d", parent.name(), cpu),
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parent, parent.systemCounter,
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irqPhys)
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{}
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ArchTimer::Interrupt irqPhys;
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ArchTimer phys;
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private:
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// Disable copying
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CoreTimers(const CoreTimers &c);
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};
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CoreTimers &getTimers(int cpu_id);
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void createTimers(unsigned cpus);
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/// System counter.
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SystemCounter systemCounter;
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/// Per-CPU physical architected timers.
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std::vector<std::unique_ptr<CoreTimers>> timers;
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protected: // Configuration
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/// Pointer to the GIC, needed to trigger timer interrupts.
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BaseGic *const gic;
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/// Physical timer interrupt
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const unsigned irqPhys;
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};
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class GenericTimerISA : public ArmISA::BaseISADevice
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{
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public:
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GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
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: parent(_parent), cpu(_cpu) {}
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void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE {
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parent.setMiscReg(misc_reg, cpu, val);
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}
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ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE {
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return parent.readMiscReg(misc_reg, cpu);
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}
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/// Ctor.
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GenericTimer(Params *p);
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/// Returns a pointer to the system counter.
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SystemCounter *getSystemCounter() { return &_systemCounter; }
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/// Returns a pointer to the architected timer for cpu_id.
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ArchTimer *getArchTimer(int cpu_id) { return &_archTimers[cpu_id]; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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protected:
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GenericTimer &parent;
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unsigned cpu;
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};
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#endif // __DEV_ARM_GENERIC_TIMER_HH__
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