dev, arm: Refactor and clean up the generic timer model
This changeset cleans up the generic timer a bit and moves most of the register juggling from the ISA code into a separate class in the same source file as the rest of the generic timer. It also removes the assumption that there is always 8 or fewer CPUs in the system. Instead of having a fixed limit, we now instantiate per-core timers as they are requested. This is all in preparation for other patches that add support for virtual timers and a memory mapped interface.
This commit is contained in:
Andreas Sandberg
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013 ARM Limited
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* Copyright (c) 2013, 2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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@@ -35,16 +35,24 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Giacomo Gabrielli
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* Andreas Sandberg
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*/
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#include "arch/arm/system.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/Timer.hh"
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#include "dev/arm/base_gic.hh"
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#include "dev/arm/generic_timer.hh"
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#include "arch/arm/system.hh"
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#include "debug/Timer.hh"
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#include "dev/arm/base_gic.hh"
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#include "params/GenericTimer.hh"
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SystemCounter::SystemCounter()
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: _freq(0), _period(0), _resetTick(0), _regCntkctl(0)
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{
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setFreq(0x01800000);
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}
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void
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GenericTimer::SystemCounter::setFreq(uint32_t freq)
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SystemCounter::setFreq(uint32_t freq)
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{
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if (_freq != 0) {
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// Altering the frequency after boot shouldn't be done in practice.
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@@ -56,147 +64,389 @@ GenericTimer::SystemCounter::setFreq(uint32_t freq)
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}
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void
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GenericTimer::SystemCounter::serialize(std::ostream &os)
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SystemCounter::serialize(std::ostream &os) const
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{
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SERIALIZE_SCALAR(_regCntkctl);
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SERIALIZE_SCALAR(_freq);
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SERIALIZE_SCALAR(_period);
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SERIALIZE_SCALAR(_resetTick);
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}
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void
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GenericTimer::SystemCounter::unserialize(Checkpoint *cp,
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const std::string §ion)
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SystemCounter::unserialize(Checkpoint *cp,
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const std::string §ion)
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{
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// We didn't handle CNTKCTL in this class before, assume it's zero
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// if it isn't present.
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if (!UNSERIALIZE_OPT_SCALAR(_regCntkctl))
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_regCntkctl = 0;
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UNSERIALIZE_SCALAR(_freq);
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UNSERIALIZE_SCALAR(_period);
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UNSERIALIZE_SCALAR(_resetTick);
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}
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ArchTimer::ArchTimer(const std::string &name,
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SimObject &parent,
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SystemCounter &sysctr,
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const Interrupt &interrupt)
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: _name(name), _parent(parent), _systemCounter(sysctr),
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_interrupt(interrupt),
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_control(0), _counterLimit(0),
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_counterLimitReachedEvent(this)
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{
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}
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void
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GenericTimer::ArchTimer::counterLimitReached()
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ArchTimer::counterLimitReached()
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{
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_control.istatus = 1;
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if (!_control.enable)
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return;
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// DPRINTF(Timer, "Counter limit reached\n");
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DPRINTF(Timer, "Counter limit reached\n");
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if (!_control.imask) {
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// DPRINTF(Timer, "Causing interrupt\n");
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_parent->_gic->sendPPInt(_intNum, _cpuNum);
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DPRINTF(Timer, "Causing interrupt\n");
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_interrupt.send();
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}
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}
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void
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GenericTimer::ArchTimer::setCompareValue(uint64_t val)
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ArchTimer::updateCounter()
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{
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_counterLimit = val;
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if (_counterLimitReachedEvent.scheduled())
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_parent->deschedule(_counterLimitReachedEvent);
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if (counterValue() >= _counterLimit) {
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_parent.deschedule(_counterLimitReachedEvent);
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if (value() >= _counterLimit) {
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counterLimitReached();
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} else {
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const auto period(_systemCounter.period());
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_control.istatus = 0;
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_parent->schedule(_counterLimitReachedEvent,
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curTick() + (_counterLimit - counterValue()) * _counter->period());
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_parent.schedule(_counterLimitReachedEvent,
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curTick() + (_counterLimit - value()) * period);
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}
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}
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void
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GenericTimer::ArchTimer::setTimerValue(uint32_t val)
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ArchTimer::setCompareValue(uint64_t val)
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{
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setCompareValue(counterValue() + sext<32>(val));
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_counterLimit = val;
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updateCounter();
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}
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void
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GenericTimer::ArchTimer::setControl(uint32_t val)
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ArchTimer::setTimerValue(uint32_t val)
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{
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setCompareValue(value() + sext<32>(val));
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}
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void
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ArchTimer::setControl(uint32_t val)
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{
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ArchTimerCtrl new_ctl = val;
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if ((new_ctl.enable && !new_ctl.imask) &&
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!(_control.enable && !_control.imask)) {
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// Re-evalute the timer condition
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if (_counterLimit >= counterValue()) {
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if (_counterLimit >= value()) {
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_control.istatus = 1;
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DPRINTF(Timer, "Causing interrupt in control\n");
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//_parent->_gic->sendPPInt(_intNum, _cpuNum);
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//_interrupt.send();
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}
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}
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_control.enable = new_ctl.enable;
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_control.imask = new_ctl.imask;
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}
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void
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GenericTimer::ArchTimer::serialize(std::ostream &os)
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uint64_t
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ArchTimer::value() const
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{
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SERIALIZE_SCALAR(_cpuNum);
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SERIALIZE_SCALAR(_intNum);
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uint32_t control_serial = _control;
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SERIALIZE_SCALAR(control_serial);
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return _systemCounter.value();
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}
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void
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ArchTimer::serialize(std::ostream &os) const
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{
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paramOut(os, "control_serial", _control);
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SERIALIZE_SCALAR(_counterLimit);
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bool event_scheduled = _counterLimitReachedEvent.scheduled();
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const bool event_scheduled(_counterLimitReachedEvent.scheduled());
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SERIALIZE_SCALAR(event_scheduled);
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Tick event_time;
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if (event_scheduled) {
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event_time = _counterLimitReachedEvent.when();
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const Tick event_time(_counterLimitReachedEvent.when());
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SERIALIZE_SCALAR(event_time);
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}
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}
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void
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GenericTimer::ArchTimer::unserialize(Checkpoint *cp, const std::string §ion)
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ArchTimer::unserialize(Checkpoint *cp,
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const std::string §ion)
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{
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UNSERIALIZE_SCALAR(_cpuNum);
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UNSERIALIZE_SCALAR(_intNum);
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uint32_t control_serial;
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UNSERIALIZE_SCALAR(control_serial);
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_control = control_serial;
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paramIn(cp, section, "control_serial", _control);
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bool event_scheduled;
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UNSERIALIZE_SCALAR(event_scheduled);
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Tick event_time;
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if (event_scheduled) {
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Tick event_time;
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UNSERIALIZE_SCALAR(event_time);
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_parent->schedule(_counterLimitReachedEvent, event_time);
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_parent.schedule(_counterLimitReachedEvent, event_time);
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}
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}
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GenericTimer::GenericTimer(Params *p)
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: SimObject(p), _gic(p->gic)
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void
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ArchTimer::Interrupt::send()
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{
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for (int i = 0; i < CPU_MAX; ++i) {
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std::stringstream oss;
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oss << name() << ".arch_timer" << i;
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_archTimers[i]._name = oss.str();
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_archTimers[i]._parent = this;
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_archTimers[i]._counter = &_systemCounter;
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_archTimers[i]._cpuNum = i;
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_archTimers[i]._intNum = p->int_num;
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}
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if (_ppi) {
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_gic.sendPPInt(_irq, _cpu);
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} else {
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_gic.sendInt(_irq);
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}
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}
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((ArmSystem *) p->system)->setGenericTimer(this);
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void
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ArchTimer::Interrupt::clear()
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{
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if (_ppi) {
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_gic.clearPPInt(_irq, _cpu);
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} else {
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_gic.clearInt(_irq);
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}
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}
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GenericTimer::GenericTimer(GenericTimerParams *p)
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: SimObject(p),
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gic(p->gic),
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irqPhys(p->int_phys)
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{
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dynamic_cast<ArmSystem &>(*p->system).setGenericTimer(this);
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}
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void
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GenericTimer::serialize(std::ostream &os)
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{
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paramOut(os, "cpu_count", timers.size());
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nameOut(os, csprintf("%s.sys_counter", name()));
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_systemCounter.serialize(os);
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for (int i = 0; i < CPU_MAX; ++i) {
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nameOut(os, csprintf("%s.arch_timer%d", name(), i));
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_archTimers[i].serialize(os);
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systemCounter.serialize(os);
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for (int i = 0; i < timers.size(); ++i) {
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CoreTimers &core(getTimers(i));
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nameOut(os, core.phys.name());
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core.phys.serialize(os);
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}
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}
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void
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GenericTimer::unserialize(Checkpoint *cp, const std::string §ion)
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{
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_systemCounter.unserialize(cp, csprintf("%s.sys_counter", section));
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for (int i = 0; i < CPU_MAX; ++i) {
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_archTimers[i].unserialize(cp, csprintf("%s.arch_timer%d", section, i));
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systemCounter.unserialize(cp, csprintf("%s.sys_counter", section));
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// Try to unserialize the CPU count. Old versions of the timer
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// model assumed a 8 CPUs, so we fall back to that if the field
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// isn't present.
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static const unsigned OLD_CPU_MAX = 8;
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unsigned cpu_count;
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if (!UNSERIALIZE_OPT_SCALAR(cpu_count)) {
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warn("Checkpoint does not contain CPU count, assuming %i CPUs\n",
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OLD_CPU_MAX);
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cpu_count = OLD_CPU_MAX;
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}
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for (int i = 0; i < cpu_count; ++i) {
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CoreTimers &core(getTimers(i));
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// This should really be phys_timerN, but we are stuck with
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// arch_timer for backwards compatibility.
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core.phys.unserialize(cp, csprintf("%s.arch_timer%d", section, i));
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}
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}
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GenericTimer::CoreTimers &
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GenericTimer::getTimers(int cpu_id)
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{
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if (cpu_id >= timers.size())
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createTimers(cpu_id + 1);
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return *timers[cpu_id];
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}
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void
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GenericTimer::createTimers(unsigned cpus)
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{
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assert(timers.size() < cpus);
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const unsigned old_cpu_count(timers.size());
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timers.resize(cpus);
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for (unsigned i = old_cpu_count; i < cpus; ++i) {
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timers[i].reset(
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new CoreTimers(*this, i, irqPhys));
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}
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}
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void
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GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
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{
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CoreTimers &core(getTimers(cpu));
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switch (reg) {
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case MISCREG_CNTFRQ:
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case MISCREG_CNTFRQ_EL0:
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systemCounter.setFreq(val);
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return;
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case MISCREG_CNTKCTL:
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case MISCREG_CNTKCTL_EL1:
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systemCounter.setKernelControl(val);
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return;
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// Physical timer
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case MISCREG_CNTP_CVAL:
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case MISCREG_CNTP_CVAL_NS:
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case MISCREG_CNTP_CVAL_EL0:
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core.phys.setCompareValue(val);
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return;
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case MISCREG_CNTP_TVAL:
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case MISCREG_CNTP_TVAL_NS:
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case MISCREG_CNTP_TVAL_EL0:
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core.phys.setTimerValue(val);
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return;
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case MISCREG_CNTP_CTL:
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case MISCREG_CNTP_CTL_NS:
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case MISCREG_CNTP_CTL_EL0:
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core.phys.setControl(val);
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return;
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// Count registers
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case MISCREG_CNTPCT:
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case MISCREG_CNTPCT_EL0:
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case MISCREG_CNTVCT:
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case MISCREG_CNTVCT_EL0:
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warn("Ignoring write to read only count register: %s\n",
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miscRegName[reg]);
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return;
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// Virtual timer
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case MISCREG_CNTVOFF:
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case MISCREG_CNTVOFF_EL2:
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case MISCREG_CNTV_CVAL:
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case MISCREG_CNTV_CVAL_EL0:
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case MISCREG_CNTV_TVAL:
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case MISCREG_CNTV_TVAL_EL0:
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case MISCREG_CNTV_CTL:
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case MISCREG_CNTV_CTL_EL0:
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/* FALLTHROUGH */
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// PL1 phys. timer, secure
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case MISCREG_CNTP_CTL_S:
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case MISCREG_CNTPS_CVAL_EL1:
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case MISCREG_CNTPS_TVAL_EL1:
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case MISCREG_CNTPS_CTL_EL1:
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/* FALLTHROUGH */
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// PL2 phys. timer, non-secure
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case MISCREG_CNTHCTL:
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case MISCREG_CNTHCTL_EL2:
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case MISCREG_CNTHP_CVAL:
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case MISCREG_CNTHP_CVAL_EL2:
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case MISCREG_CNTHP_TVAL:
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case MISCREG_CNTHP_TVAL_EL2:
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case MISCREG_CNTHP_CTL:
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case MISCREG_CNTHP_CTL_EL2:
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warn("Writing to unimplemented register: %s\n",
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miscRegName[reg]);
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return;
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default:
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warn("Writing to unknown register: %s\n", miscRegName[reg]);
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return;
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}
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}
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MiscReg
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GenericTimer::readMiscReg(int reg, unsigned cpu)
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{
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CoreTimers &core(getTimers(cpu));
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switch (reg) {
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case MISCREG_CNTFRQ:
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case MISCREG_CNTFRQ_EL0:
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return systemCounter.freq();
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case MISCREG_CNTKCTL:
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case MISCREG_CNTKCTL_EL1:
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return systemCounter.getKernelControl();
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// Physical timer
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case MISCREG_CNTP_CVAL:
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case MISCREG_CNTP_CVAL_EL0:
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return core.phys.compareValue();
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case MISCREG_CNTP_TVAL:
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case MISCREG_CNTP_TVAL_EL0:
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return core.phys.timerValue();
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case MISCREG_CNTP_CTL:
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case MISCREG_CNTP_CTL_EL0:
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case MISCREG_CNTP_CTL_NS:
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return core.phys.control();
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case MISCREG_CNTPCT:
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case MISCREG_CNTPCT_EL0:
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return core.phys.value();
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// Virtual timer
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case MISCREG_CNTVCT:
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case MISCREG_CNTVCT_EL0:
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warn_once("Virtual timer not implemented, "
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"returning physical timer value\n");
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return core.phys.value();
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case MISCREG_CNTVOFF:
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case MISCREG_CNTVOFF_EL2:
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case MISCREG_CNTV_CVAL:
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case MISCREG_CNTV_CVAL_EL0:
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case MISCREG_CNTV_TVAL:
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case MISCREG_CNTV_TVAL_EL0:
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case MISCREG_CNTV_CTL:
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case MISCREG_CNTV_CTL_EL0:
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/* FALLTHROUGH */
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// PL1 phys. timer, secure
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case MISCREG_CNTP_CTL_S:
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case MISCREG_CNTPS_CVAL_EL1:
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case MISCREG_CNTPS_TVAL_EL1:
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case MISCREG_CNTPS_CTL_EL1:
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/* FALLTHROUGH */
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// PL2 phys. timer, non-secure
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case MISCREG_CNTHCTL:
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case MISCREG_CNTHCTL_EL2:
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case MISCREG_CNTHP_CVAL:
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case MISCREG_CNTHP_CVAL_EL2:
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case MISCREG_CNTHP_TVAL:
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case MISCREG_CNTHP_TVAL_EL2:
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case MISCREG_CNTHP_CTL:
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case MISCREG_CNTHP_CTL_EL2:
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warn("Reading from unimplemented register: %s\n",
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miscRegName[reg]);
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return 0;
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default:
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warn("Reading from unknown register: %s\n", miscRegName[reg]);
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return 0;
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}
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}
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GenericTimer *
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GenericTimerParams::create()
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{
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