stdlib: Move 'connect_things' to the AbstractBoard

This is in order to enforce a strict ordering of how gem5 components are
incorporated into a board. The `connect_things` function is now final so
it cannot be overridden.

Change-Id: I4c0e7ac9d307b399854f5326bb57bcf561f92054
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52183
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

src/python/gem5/components/boards/abstract_board.py

@@ -37,7 +37,7 @@ from m5.objects import (
     VoltageDomain,
 )
 
-from typing import List
+from typing import List, final
 
 
 class AbstractBoard(System):
@@ -219,15 +219,24 @@ class AbstractBoard(System):
         """
         raise NotImplementedError
 
-    @abstractmethod
+    @final
     def connect_things(self) -> None:
         """Connects all the components to the board.
 
-        This should be called after the constructor.
+        The order of this board is always:
 
-        When implementing this function, derived boards should use this to
-        hook up the memory, process, and cache hierarchy as a *second* stage.
-        You should use this function to connect things together when you need
-        to know that everything has already been constructed.
+        1. Connect the memory.
+        2. Connect the processor.
+        3. Connect the cache hierarchy.
+
+        Developers may build upon this assumption when creating components.
         """
-        raise NotImplementedError
+
+        # Incorporate the memory into the motherboard.
+        self.get_memory().incorporate_memory(self)
+
+        # Incorporate the processor into the motherboard.
+        self.get_processor().incorporate_processor(self)
+
+        # Incorporate the cache hierarchy for the motherboard.
+        self.get_cache_hierarchy().incorporate_cache(self)

src/python/gem5/components/boards/riscv_board.py

@@ -123,6 +123,9 @@ class RiscvBoard(AbstractBoard, KernelDiskWorkload):
         self._on_chip_devices = [self.platform.clint, self.platform.plic]
         self._off_chip_devices = [self.platform.uart, self.disk]
 
+        # Set up the memory ranges
+        self.setup_memory_ranges()
+
     def _setup_io_devices(self) -> None:
         """Connect the I/O devices to the I/O bus"""
 
@@ -192,20 +195,6 @@ class RiscvBoard(AbstractBoard, KernelDiskWorkload):
         self.mem_ranges = [AddrRange(start=0x80000000, size=mem_size)]
         memory.set_memory_range(self.mem_ranges)
 
-    @overrides(AbstractBoard)
-    def connect_things(self) -> None:
-        # Before incorporating the memory, set up the memory ranges
-        self.setup_memory_ranges()
-
-        # Incorporate the cache hierarchy for the motherboard.
-        self.get_cache_hierarchy().incorporate_cache(self)
-
-        # Incorporate the processor into the motherboard.
-        self.get_processor().incorporate_processor(self)
-
-        # Incorporate the memory into the motherboard.
-        self.get_memory().incorporate_memory(self)
-
     def generate_device_tree(self, outdir: str) -> None:
         """Creates the dtb and dts files.
 

src/python/gem5/components/boards/simple_board.py

@@ -72,16 +72,8 @@ class SimpleBoard(AbstractBoard):
             exit_on_work_items=exit_on_work_items,
         )
 
-    @overrides(AbstractBoard)
-    def connect_things(self) -> None:
-        # Incorporate the cache hierarchy for the motherboard.
-        self.get_cache_hierarchy().incorporate_cache(self)
-
-        # Incorporate the processor into the motherboard.
-        self.get_processor().incorporate_processor(self)
-
-        # Incorporate the memory into the motherboard.
-        self.get_memory().incorporate_memory(self)
+        # Set up the memory ranges
+        self.setup_memory_ranges()
 
     @overrides(AbstractBoard)
     def has_io_bus(self) -> bool:

src/python/gem5/components/boards/test_board.py

@@ -66,12 +66,7 @@ class TestBoard(AbstractBoard):
             cache_hierarchy=cache_hierarchy,
         )
 
-    def connect_things(self) -> None:
-        self.get_processor().incorporate_processor(self)
-
-        self.get_memory().incorporate_memory(self)
-
-        self.get_cache_hierarchy().incorporate_cache(self)
+        self.setup_memory_ranges()
 
     @overrides(AbstractBoard)
     def has_io_bus(self) -> bool:

src/python/gem5/components/boards/x86_board.py

@@ -97,6 +97,12 @@ class X86Board(AbstractBoard, KernelDiskWorkload):
         # North Bridge
         self.iobus = IOXBar()
 
+        # Figure out the memory ranges.
+        self.setup_memory_ranges()
+
+        # Set up all of the I/O.
+        self._setup_io_devices()
+
     def _setup_io_devices(self):
         """ Sets up the x86 IO devices.
 
@@ -246,22 +252,6 @@ class X86Board(AbstractBoard, KernelDiskWorkload):
 
         self.workload.e820_table.entries = entries
 
-    def connect_things(self) -> None:
-        # This board is a bit particular about the order that things are
-        # connected together.
-
-        # Set up all of the I/O before we incorporate anything else.
-        self._setup_io_devices()
-
-        # Incorporate the cache hierarchy for the motherboard.
-        self.get_cache_hierarchy().incorporate_cache(self)
-
-        # Incorporate the processor into the motherboard.
-        self.get_processor().incorporate_processor(self)
-
-        # Incorporate the memory into the motherboard.
-        self.get_memory().incorporate_memory(self)
-
     @overrides(AbstractBoard)
     def has_io_bus(self) -> bool:
         return True