From 651de2d9af8ac628b69b40812ff036231da40ae3 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 26 Oct 2012 06:42:42 -0400 Subject: [PATCH] config: Fix the cache class naming in regression scripts This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts. --- configs/common/Caches.py | 5 ++--- tests/configs/o3-timing-mp.py | 6 +++--- tests/configs/pc-o3-timing.py | 6 +++--- tests/configs/pc-simple-atomic.py | 6 +++--- tests/configs/pc-simple-timing.py | 6 +++--- tests/configs/realview-o3-checker.py | 6 +++--- tests/configs/realview-o3-dual.py | 6 +++--- tests/configs/realview-o3.py | 6 +++--- tests/configs/realview-simple-atomic-dual.py | 6 +++--- tests/configs/realview-simple-atomic.py | 6 +++--- tests/configs/realview-simple-timing-dual.py | 6 +++--- tests/configs/realview-simple-timing.py | 6 +++--- tests/configs/tsunami-inorder.py | 6 +++--- tests/configs/tsunami-o3-dual.py | 6 +++--- tests/configs/tsunami-o3.py | 6 +++--- tests/configs/tsunami-simple-atomic-dual.py | 6 +++--- tests/configs/tsunami-simple-atomic.py | 6 +++--- tests/configs/tsunami-simple-timing-dual.py | 6 +++--- tests/configs/tsunami-simple-timing.py | 6 +++--- 19 files changed, 56 insertions(+), 57 deletions(-) diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 867d0cb2e2..e6cbb1a75b 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -46,7 +46,7 @@ from m5.objects import * # starting point, and specific parameters can be overridden in the # specific instantiations. -class L1(BaseCache): +class L1Cache(BaseCache): assoc = 2 hit_latency = 2 response_latency = 2 @@ -55,7 +55,7 @@ class L1(BaseCache): tgts_per_mshr = 20 is_top_level = True -class L2(BaseCache): +class L2Cache(BaseCache): assoc = 8 block_size = 64 hit_latency = 20 @@ -84,4 +84,3 @@ class PageTableWalkerCache(BaseCache): size = '1kB' tgts_per_mshr = 12 is_top_level = True - diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 2b611fb9d3..6f3bddc6f0 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -39,7 +39,7 @@ system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus()) # l2cache & bus system.toL2Bus = CoherentBus(clock = '2GHz') -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -47,8 +47,8 @@ system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: - cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index c4317ec23e..6bab4c448f 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8), +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8), PageTableWalkerCache(), PageTableWalkerCache()) # create the interrupt controller diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py index 44ba51b3c1..74d47fe417 100644 --- a/tests/configs/pc-simple-atomic.py +++ b/tests/configs/pc-simple-atomic.py @@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8), +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8), PageTableWalkerCache(), PageTableWalkerCache()) # create the interrupt controller diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 9901790083..1b7e809f71 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8), +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8), PageTableWalkerCache(), PageTableWalkerCache()) # create the interrupt controller diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py index 248a1d41b2..8c5d4086da 100644 --- a/tests/configs/realview-o3-checker.py +++ b/tests/configs/realview-o3-checker.py @@ -56,9 +56,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index cc4fa236fb..b5c235a675 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -46,14 +46,14 @@ system.cpu = cpus system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 6f98309fe8..6dbc0c828b 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py index b26272a910..90a9d55379 100644 --- a/tests/configs/realview-simple-atomic-dual.py +++ b/tests/configs/realview-simple-atomic-dual.py @@ -46,14 +46,14 @@ system.cpu = cpus system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index 2d1efe3fe8..5cad3a2cbf 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 1c86f42bfc..5b8e6e0e3d 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -46,14 +46,14 @@ system.cpu = cpus system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index 4bb641e808..c2dc27b486 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py index 0d7e817e0f..b0aa1c7cda 100644 --- a/tests/configs/tsunami-inorder.py +++ b/tests/configs/tsunami-inorder.py @@ -48,9 +48,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index a1564f8f8d..9aac5e744c 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -46,14 +46,14 @@ system.iocache.mem_side = system.membus.slave #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index 18cbf1db1d..d50b592579 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 1f63ff7a84..b91d56cec3 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -45,14 +45,14 @@ system.cpu = cpus system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 9c7e5c265d..bbab929cdf 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 8bac5bd903..4d74d90575 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -45,14 +45,14 @@ system.cpu = cpus system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 60b4e47f47..7bba6f938a 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system