tests: Reflect name change in DRAM tests

This patch reflects the recent name change in the DRAM TrafficGen
tests and also tidies up the test directory.

--HG--
rename : tests/configs/tgen-simple-dram.py => tests/configs/tgen-dram-ctrl.py
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
rename : tests/quick/se/70.tgen/tgen-simple-dram.cfg => tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
This commit is contained in:
Andreas Hansson
2014-05-09 18:58:49 -04:00
parent f800f268db
commit 64806c4c13
14 changed files with 14 additions and 63 deletions

View File

@@ -334,7 +334,7 @@ if env['TARGET_ISA'] == 'x86':
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
'inorder-timing', 'rubytest', 'tgen-simple-mem',
'tgen-simple-dram']
'tgen-dram-ctrl']
if env['PROTOCOL'] != 'None':
if env['PROTOCOL'] == 'MI_example':