From 64168fd4ea53880b946a714ba7f81ac192f3f1dd Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 1 Aug 2021 10:25:57 -0700 Subject: [PATCH] scons: Turn the ISA and GPU ISA lists into construction variables. Change-Id: I4135709f5bceee959b5178a4700656aa782b1d6b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48965 Maintainer: Gabe Black Tested-by: kokoro Reviewed-by: Bobby R. Bruce --- src/SConscript | 8 ++++---- src/arch/SConsopts | 12 +++--------- src/arch/amdgpu/gcn3/SConsopts | 2 +- src/arch/amdgpu/vega/SConsopts | 2 +- src/arch/arm/SConsopts | 2 +- src/arch/mips/SConsopts | 2 +- src/arch/null/SConsopts | 2 +- src/arch/power/SConsopts | 2 +- src/arch/riscv/SConsopts | 2 +- src/arch/sparc/SConsopts | 2 +- src/arch/x86/SConsopts | 2 +- src/cpu/SConsopts | 7 +------ src/cpu/checker/SConsopts | 2 +- src/cpu/minor/SConsopts | 2 +- src/cpu/o3/SConsopts | 2 +- src/cpu/simple/SConsopts | 3 +-- 16 files changed, 21 insertions(+), 33 deletions(-) diff --git a/src/SConscript b/src/SConscript index 7ea946b901..bc19ac9844 100644 --- a/src/SConscript +++ b/src/SConscript @@ -709,7 +709,7 @@ for opt in export_vars: env.ConfigFile(opt) def makeTheISA(source, target, env): - isas = [ src.get_contents().decode('utf-8') for src in source ] + isas = sorted(set(env.Split('${ALL_ISAS}'))) target_isa = env['TARGET_ISA'] is_null_isa = '1' if (target_isa.lower() == 'null') else '0' @@ -740,11 +740,11 @@ def makeTheISA(source, target, env): code.write(str(target[0])) -env.Command('config/the_isa.hh', list(map(Value, all_isa_list)), +env.Command('config/the_isa.hh', [], MakeAction(makeTheISA, Transform("CFG ISA", 0))) def makeTheGPUISA(source, target, env): - isas = [ src.get_contents().decode('utf-8') for src in source ] + isas = sorted(set(env.Split('${ALL_ISAS}'))) target_gpu_isa = env['TARGET_GPU_ISA'] def define(isa): return str(isa.upper()) + '_ISA' @@ -782,7 +782,7 @@ def makeTheGPUISA(source, target, env): code.write(str(target[0])) -env.Command('config/the_gpu_isa.hh', list(map(Value, all_gpu_isa_list)), +env.Command('config/the_gpu_isa.hh', [], MakeAction(makeTheGPUISA, Transform("CFG ISA", 0))) ######################################################################## diff --git a/src/arch/SConsopts b/src/arch/SConsopts index 90ac93b00d..38b02f51f5 100644 --- a/src/arch/SConsopts +++ b/src/arch/SConsopts @@ -25,18 +25,12 @@ Import('*') -# Define the universe of supported ISAs -all_isa_list = [] -Export('all_isa_list') - -all_gpu_isa_list = [] -Export('all_gpu_isa_list') - def add_isa_lists(): sticky_vars.AddVariables( - EnumVariable('TARGET_ISA', 'Target ISA', 'null', sorted(all_isa_list)), + EnumVariable('TARGET_ISA', 'Target ISA', 'null', + sorted(set(main.Split('${ALL_ISAS}')))), EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'gcn3', - sorted(all_gpu_isa_list)), + sorted(set(main.Split('${ALL_GPU_ISAS}')))), ) AfterSConsopts(add_isa_lists) diff --git a/src/arch/amdgpu/gcn3/SConsopts b/src/arch/amdgpu/gcn3/SConsopts index 92bde9755a..3312e98082 100644 --- a/src/arch/amdgpu/gcn3/SConsopts +++ b/src/arch/amdgpu/gcn3/SConsopts @@ -33,4 +33,4 @@ Import('*') -all_gpu_isa_list.append('gcn3') +main.Append(ALL_GPU_ISAS=['gcn3']) diff --git a/src/arch/amdgpu/vega/SConsopts b/src/arch/amdgpu/vega/SConsopts index 0e44e37ec0..b2b6695722 100644 --- a/src/arch/amdgpu/vega/SConsopts +++ b/src/arch/amdgpu/vega/SConsopts @@ -33,4 +33,4 @@ Import('*') -all_gpu_isa_list.append('vega') +main.Append(ALL_GPU_ISAS=['vega']) diff --git a/src/arch/arm/SConsopts b/src/arch/arm/SConsopts index 020e4995a9..c284f2c4b7 100644 --- a/src/arch/arm/SConsopts +++ b/src/arch/arm/SConsopts @@ -28,4 +28,4 @@ Import('*') -all_isa_list.append('arm') +main.Append(ALL_ISAS=['arm']) diff --git a/src/arch/mips/SConsopts b/src/arch/mips/SConsopts index ee4d236745..58240c1d9f 100644 --- a/src/arch/mips/SConsopts +++ b/src/arch/mips/SConsopts @@ -28,4 +28,4 @@ Import('*') -all_isa_list.append('mips') +main.Append(ALL_ISAS=['mips']) diff --git a/src/arch/null/SConsopts b/src/arch/null/SConsopts index a7997540a3..6355ce314b 100644 --- a/src/arch/null/SConsopts +++ b/src/arch/null/SConsopts @@ -37,4 +37,4 @@ Import('*') -all_isa_list.append('null') +main.Append(ALL_ISAS=['null']) diff --git a/src/arch/power/SConsopts b/src/arch/power/SConsopts index 851f2babb4..cb136fe777 100644 --- a/src/arch/power/SConsopts +++ b/src/arch/power/SConsopts @@ -28,4 +28,4 @@ Import('*') -all_isa_list.append('power') +main.Append(ALL_ISAS=['power']) diff --git a/src/arch/riscv/SConsopts b/src/arch/riscv/SConsopts index f5a8de56b4..76713ee13d 100644 --- a/src/arch/riscv/SConsopts +++ b/src/arch/riscv/SConsopts @@ -28,4 +28,4 @@ Import('*') -all_isa_list.append('riscv') +main.Append(ALL_ISAS=['riscv']) diff --git a/src/arch/sparc/SConsopts b/src/arch/sparc/SConsopts index 41aa275d1e..48fb4a6e62 100644 --- a/src/arch/sparc/SConsopts +++ b/src/arch/sparc/SConsopts @@ -28,4 +28,4 @@ Import('*') -all_isa_list.append('sparc') +main.Append(ALL_ISAS=['sparc']) diff --git a/src/arch/x86/SConsopts b/src/arch/x86/SConsopts index 006d00973b..93dff8ca5a 100644 --- a/src/arch/x86/SConsopts +++ b/src/arch/x86/SConsopts @@ -28,4 +28,4 @@ Import('*') -all_isa_list.append('x86') +main.Append(ALL_ISAS=['x86']) diff --git a/src/cpu/SConsopts b/src/cpu/SConsopts index af35a20cdb..c39d1eb010 100644 --- a/src/cpu/SConsopts +++ b/src/cpu/SConsopts @@ -25,12 +25,7 @@ Import('*') -def CpuModel(name): - main.Append(ALL_CPU_MODELS=[name]) - -Export('CpuModel') - def add_cpu_models_var(): sticky_vars.Add(ListVariable('CPU_MODELS', 'CPU models', [], - set(main.get('ALL_CPU_MODELS', [])))) + sorted(set(main.Split('${ALL_CPU_MODELS}'))))) AfterSConsopts(add_cpu_models_var) diff --git a/src/cpu/checker/SConsopts b/src/cpu/checker/SConsopts index f949d2a874..5a7a873819 100644 --- a/src/cpu/checker/SConsopts +++ b/src/cpu/checker/SConsopts @@ -28,4 +28,4 @@ Import('*') -CpuModel('CheckerCPU') +main.Append(ALL_CPU_MODELS=['CheckerCPU']) diff --git a/src/cpu/minor/SConsopts b/src/cpu/minor/SConsopts index 9169ee9cda..16ff599cb6 100644 --- a/src/cpu/minor/SConsopts +++ b/src/cpu/minor/SConsopts @@ -37,4 +37,4 @@ Import('*') -CpuModel('MinorCPU') +main.Append(ALL_CPU_MODELS=['MinorCPU']) diff --git a/src/cpu/o3/SConsopts b/src/cpu/o3/SConsopts index 0c0c56c0ee..3479484f16 100644 --- a/src/cpu/o3/SConsopts +++ b/src/cpu/o3/SConsopts @@ -28,4 +28,4 @@ Import('*') -CpuModel('O3CPU') +main.Append(ALL_CPU_MODELS=['O3CPU']) diff --git a/src/cpu/simple/SConsopts b/src/cpu/simple/SConsopts index 5ebdf3093d..f12fee2b78 100644 --- a/src/cpu/simple/SConsopts +++ b/src/cpu/simple/SConsopts @@ -28,5 +28,4 @@ Import('*') -CpuModel('AtomicSimpleCPU') -CpuModel('TimingSimpleCPU') +main.Append(ALL_CPU_MODELS=['AtomicSimpleCPU', 'TimingSimpleCPU'])