From 63ea52de56277db01effdf93625ed23011f202d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sa=C3=BAl?= <33020671+saul44203@users.noreply.github.com> Date: Tue, 5 Nov 2024 21:13:51 +0100 Subject: [PATCH] arch-riscv: fix vrgather pin count (#1759) The number of register pins for the vector gather instructions was not calculated correctly because the micro vl was not right. This caused some micros to rename a new register instead of using a pinned one. --- src/arch/riscv/isa/templates/vector_arith.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/isa/templates/vector_arith.isa b/src/arch/riscv/isa/templates/vector_arith.isa index 4944b5cc75..f11581094b 100644 --- a/src/arch/riscv/isa/templates/vector_arith.isa +++ b/src/arch/riscv/isa/templates/vector_arith.isa @@ -1961,7 +1961,7 @@ template uint32_t vd_vlmax = vlenb / vd_eewb; uint32_t vs1_vlmax = vlenb / vs1_eewb; for (uint32_t i = 0; i < ceil((float) this->vl / vd_vlmax); i++) { - uint32_t pinvd_micro_vl = (vd_vlmax*(i+1) <= remaining_vl) + uint32_t pinvd_micro_vl = (vd_vlmax <= remaining_vl) ? vd_vlmax : remaining_vl; uint8_t num_vd_pins = ceil((float) pinvd_micro_vl/vs1_vlmax)*vs2_vregs; microop = new VPinVdMicroInst(machInst, i, num_vd_pins, elen, vlen);