From 639e407270247729d3b462590567ed4f4ddefc74 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 20 Jul 2022 14:46:52 -0700 Subject: [PATCH] arch-mips,cpu-minor: Add MinorCPU to X86 ISA While it may not be well supported, it's better to incorporate the MinorCPU into the X86 ISA gem5 binary than leave it out. Change-Id: I98d015c23e347276f6b943291877dc15026eb0da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61539 Reviewed-by: Bobby Bruce Tested-by: kokoro Maintainer: Bobby Bruce --- src/arch/x86/X86CPU.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/arch/x86/X86CPU.py b/src/arch/x86/X86CPU.py index 7ea2adf6a8..db4e4d0a3f 100644 --- a/src/arch/x86/X86CPU.py +++ b/src/arch/x86/X86CPU.py @@ -29,6 +29,7 @@ from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseMinorCPU import BaseMinorCPU from m5.objects.X86Decoder import X86Decoder from m5.objects.X86MMU import X86MMU from m5.objects.X86LocalApic import X86LocalApic @@ -65,3 +66,7 @@ class X86O3CPU(BaseO3CPU, X86CPU): # (it's a side effect of int reg renaming), so they should # never be the bottleneck here. numPhysCCRegs = Self.numPhysIntRegs * 5 + + +class X86MinorCPU(BaseMinorCPU, X86CPU): + mmu = X86MMU()