From 62ce119139a4f400095cdcf1e9fc720165003cf2 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 12 Oct 2022 18:51:31 +0100 Subject: [PATCH] arch-arm: Always use AArch64 version of HCR/SCR We are slowly replacing AArch32 code in favour of AArch64. Change-Id: I2857a198a0169e882e5f997debc76808244ab42d Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64911 Reviewed-by: Andreas Sandberg Tested-by: kokoro Maintainer: Andreas Sandberg --- src/arch/arm/faults.cc | 56 ++++++++++++------------------------ src/arch/arm/insts/misc.cc | 52 ++++++++++++++++----------------- src/arch/arm/insts/misc64.cc | 52 ++++++++++++++++----------------- src/arch/arm/interrupts.cc | 11 ++----- src/arch/arm/interrupts.hh | 4 +-- src/arch/arm/isa.cc | 18 ++++-------- src/arch/arm/mmu.cc | 4 +-- src/arch/arm/regs/misc.cc | 4 +-- src/arch/arm/utility.cc | 25 +++++++--------- 9 files changed, 94 insertions(+), 132 deletions(-) diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index d2696a2fe7..b4ef199201 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -514,7 +514,7 @@ ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst) return; SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); saved_cpsr.nz = tc->getReg(cc_reg::Nz); saved_cpsr.c = tc->getReg(cc_reg::C); @@ -533,10 +533,10 @@ ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst) // Ensure Secure state if initially in Monitor mode if (have_security && saved_cpsr.mode == MODE_MON) { - SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); if (scr.ns) { scr.ns = 0; - tc->setMiscRegNoEffect(MISCREG_SCR, scr); + tc->setMiscRegNoEffect(MISCREG_SCR_EL3, scr); } } @@ -827,7 +827,7 @@ UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) bool UndefinedInstruction::routeToHyp(ThreadContext *tc) const { - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); return fromEL == EL2 || (EL2Enabled(tc) && (fromEL == EL0) && hcr.tge); } @@ -883,7 +883,7 @@ SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) bool SupervisorCall::routeToHyp(ThreadContext *tc) const { - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); return fromEL == EL2 || (EL2Enabled(tc) && fromEL == EL0 && hcr.tge); } @@ -1212,7 +1212,7 @@ bool AbortFault::abortDisable(ThreadContext *tc) { if (ArmSystem::haveEL(tc, EL3)) { - SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return (!scr.ns || scr.aw); } return true; @@ -1302,12 +1302,7 @@ PrefetchAbort::iss() const bool PrefetchAbort::routeToMonitor(ThreadContext *tc) const { - SCR scr = 0; - if (from64) - scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); - else - scr = tc->readMiscRegNoEffect(MISCREG_SCR); - + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return scr.ea && !isMMUFault(); } @@ -1316,7 +1311,7 @@ PrefetchAbort::routeToHyp(ThreadContext *tc) const { bool toHyp; - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); toHyp = fromEL == EL2; @@ -1364,12 +1359,7 @@ DataAbort::il(ThreadContext *tc) const bool DataAbort::routeToMonitor(ThreadContext *tc) const { - SCR scr = 0; - if (from64) - scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); - else - scr = tc->readMiscRegNoEffect(MISCREG_SCR); - + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return scr.ea && !isMMUFault(); } @@ -1378,7 +1368,7 @@ DataAbort::routeToHyp(ThreadContext *tc) const { bool toHyp; - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); bool amo = hcr.amo; @@ -1467,27 +1457,23 @@ void VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) { AbortFault::invoke(tc, inst); - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); hcr.va = 0; - tc->setMiscRegNoEffect(MISCREG_HCR, hcr); + tc->setMiscRegNoEffect(MISCREG_HCR_EL2, hcr); } bool Interrupt::routeToMonitor(ThreadContext *tc) const { assert(ArmSystem::haveEL(tc, EL3)); - SCR scr = 0; - if (from64) - scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); - else - scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return scr.irq; } bool Interrupt::routeToHyp(ThreadContext *tc) const { - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo)); } @@ -1496,7 +1482,7 @@ bool Interrupt::abortDisable(ThreadContext *tc) { if (ArmSystem::haveEL(tc, EL3)) { - SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return (!scr.ns || scr.aw); } return true; @@ -1509,18 +1495,14 @@ bool FastInterrupt::routeToMonitor(ThreadContext *tc) const { assert(ArmSystem::haveEL(tc, EL3)); - SCR scr = 0; - if (from64) - scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); - else - scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return scr.fiq; } bool FastInterrupt::routeToHyp(ThreadContext *tc) const { - HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo)); } @@ -1529,7 +1511,7 @@ bool FastInterrupt::abortDisable(ThreadContext *tc) { if (ArmSystem::haveEL(tc, EL3)) { - SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return (!scr.ns || scr.aw); } return true; @@ -1541,7 +1523,7 @@ FastInterrupt::fiqDisable(ThreadContext *tc) if (ArmSystem::haveEL(tc, EL2)) { return true; } else if (ArmSystem::haveEL(tc, EL3)) { - SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); + SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); return (!scr.ns || scr.fw); } return true; diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 97a1b8b3ac..546d2caebb 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -408,7 +408,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const switch (dest_idx) { case MISCREG_TLBIALL: // TLBI all entries, EL0&1, { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIALL tlbiOp(EL1, secure); @@ -418,7 +418,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate All, Inner Shareable case MISCREG_TLBIALLIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIALL tlbiOp(EL1, secure); @@ -428,7 +428,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Instruction TLB Invalidate All case MISCREG_ITLBIALL: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; ITLBIALL tlbiOp(EL1, secure); @@ -438,7 +438,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Data TLB Invalidate All case MISCREG_DTLBIALL: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; DTLBIALL tlbiOp(EL1, secure); @@ -448,7 +448,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA case MISCREG_TLBIMVA: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVA tlbiOp(EL1, @@ -463,7 +463,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Last Level case MISCREG_TLBIMVAL: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVA tlbiOp(EL1, @@ -478,7 +478,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Inner Shareable case MISCREG_TLBIMVAIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVA tlbiOp(EL1, @@ -493,7 +493,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Last Level, Inner Shareable case MISCREG_TLBIMVALIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVA tlbiOp(EL1, @@ -508,7 +508,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by ASID match case MISCREG_TLBIASID: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIASID tlbiOp(EL1, @@ -521,7 +521,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by ASID match, Inner Shareable case MISCREG_TLBIASIDIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIASID tlbiOp(EL1, @@ -534,7 +534,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, All ASID case MISCREG_TLBIMVAA: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL1, secure, @@ -546,7 +546,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Last Level, All ASID case MISCREG_TLBIMVAAL: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL1, secure, @@ -558,7 +558,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, All ASID, Inner Shareable case MISCREG_TLBIMVAAIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL1, secure, @@ -570,7 +570,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, All ASID, Last Level, Inner Shareable case MISCREG_TLBIMVAALIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL1, secure, @@ -582,7 +582,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Hyp mode case MISCREG_TLBIMVAH: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL2, secure, @@ -594,7 +594,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Last Level, Hyp mode case MISCREG_TLBIMVALH: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL2, secure, @@ -606,7 +606,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Hyp mode, Inner Shareable case MISCREG_TLBIMVAHIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL2, secure, @@ -618,7 +618,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by VA, Hyp mode, Last Level, Inner Shareable case MISCREG_TLBIMVALHIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIMVAA tlbiOp(EL2, secure, @@ -630,7 +630,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // TLB Invalidate by Intermediate Physical Address, Stage 2 case MISCREG_TLBIIPAS2: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIIPA tlbiOp(EL1, @@ -645,7 +645,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Last Level case MISCREG_TLBIIPAS2L: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIIPA tlbiOp(EL1, @@ -660,7 +660,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Inner Shareable case MISCREG_TLBIIPAS2IS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIIPA tlbiOp(EL1, @@ -675,7 +675,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Last Level, Inner Shareable case MISCREG_TLBIIPAS2LIS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIIPA tlbiOp(EL1, @@ -689,7 +689,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Instruction TLB Invalidate by VA case MISCREG_ITLBIMVA: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; ITLBIMVA tlbiOp(EL1, @@ -703,7 +703,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Data TLB Invalidate by VA case MISCREG_DTLBIMVA: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; DTLBIMVA tlbiOp(EL1, @@ -717,7 +717,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Instruction TLB Invalidate by ASID match case MISCREG_ITLBIASID: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; ITLBIASID tlbiOp(EL1, @@ -730,7 +730,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const // Data TLB Invalidate by ASID match case MISCREG_DTLBIASID: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; DTLBIASID tlbiOp(EL1, diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 0fde0770fb..40a6ca4ce5 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -249,7 +249,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate All, EL2 case MISCREG_TLBI_ALLE2: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIALLEL tlbiOp(EL2, secure); @@ -259,7 +259,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate All, EL2, Inner Shareable case MISCREG_TLBI_ALLE2IS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIALLEL tlbiOp(EL2, secure); @@ -269,7 +269,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate All, EL1 case MISCREG_TLBI_ALLE1: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIALLEL tlbiOp(EL1, secure); @@ -279,7 +279,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate All, EL1, Inner Shareable case MISCREG_TLBI_ALLE1IS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIALLEL tlbiOp(EL1, secure); @@ -288,7 +288,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons } case MISCREG_TLBI_VMALLS12E1: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIVMALL tlbiOp(EL1, secure, true); @@ -297,7 +297,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons } case MISCREG_TLBI_VMALLE1: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); ExceptionLevel target_el = EL1; if (EL2Enabled(tc)) { @@ -314,7 +314,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons } case MISCREG_TLBI_VMALLS12E1IS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; TLBIVMALL tlbiOp(EL1, secure, true); @@ -323,7 +323,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons } case MISCREG_TLBI_VMALLE1IS: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); ExceptionLevel target_el = EL1; if (EL2Enabled(tc)) { @@ -381,7 +381,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, EL2 case MISCREG_TLBI_VAE2_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; @@ -406,7 +406,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, Last Level, EL2 case MISCREG_TLBI_VALE2_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; @@ -431,7 +431,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, EL2, Inner Shareable case MISCREG_TLBI_VAE2IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; @@ -456,7 +456,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, Last Level, EL2, Inner Shareable case MISCREG_TLBI_VALE2IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; @@ -481,7 +481,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, EL1 case MISCREG_TLBI_VAE1_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); @@ -504,7 +504,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, Last Level, EL1 case MISCREG_TLBI_VALE1_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); @@ -527,7 +527,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, EL1, Inner Shareable case MISCREG_TLBI_VAE1IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); @@ -549,7 +549,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons } case MISCREG_TLBI_VALE1IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); @@ -572,7 +572,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by ASID, EL1 case MISCREG_TLBI_ASIDE1_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); @@ -592,7 +592,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable case MISCREG_TLBI_ASIDE1IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); @@ -612,7 +612,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, All ASID, EL1 case MISCREG_TLBI_VAAE1_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); ExceptionLevel target_el = EL1; if (EL2Enabled(tc)) { @@ -633,7 +633,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, Last Level, All ASID, EL1 case MISCREG_TLBI_VAALE1_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); ExceptionLevel target_el = EL1; if (EL2Enabled(tc)) { @@ -654,7 +654,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable case MISCREG_TLBI_VAAE1IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); ExceptionLevel target_el = EL1; if (EL2Enabled(tc)) { @@ -676,7 +676,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons // Last Level, EL1, Inner Shareable case MISCREG_TLBI_VAALE1IS_Xt: { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); ExceptionLevel target_el = EL1; if (EL2Enabled(tc)) { @@ -699,7 +699,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons case MISCREG_TLBI_IPAS2E1_Xt: { if (EL2Enabled(tc)) { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns && !bits(value, 63); @@ -719,7 +719,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons case MISCREG_TLBI_IPAS2LE1_Xt: { if (EL2Enabled(tc)) { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns && !bits(value, 63); @@ -737,7 +737,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons case MISCREG_TLBI_IPAS2E1IS_Xt: { if (EL2Enabled(tc)) { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns && !bits(value, 63); @@ -757,7 +757,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons case MISCREG_TLBI_IPAS2LE1IS_Xt: { if (EL2Enabled(tc)) { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); bool secure = release->has(ArmExtension::SECURITY) && !scr.ns && !bits(value, 63); diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc index b0f18dfe3f..57b1334b77 100644 --- a/src/arch/arm/interrupts.cc +++ b/src/arch/arm/interrupts.cc @@ -50,17 +50,10 @@ ArmISA::Interrupts::takeInt(InterruptTypes int_type) const bool highest_el_is_64 = ArmSystem::highestELIs64(tc); CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); - SCR scr; - HCR hcr; - hcr = tc->readMiscReg(MISCREG_HCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);; + HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); ExceptionLevel el = currEL(tc); bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit; - - if (!highest_el_is_64) - scr = tc->readMiscReg(MISCREG_SCR); - else - scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool is_secure = isSecure(tc); switch(int_type) { diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh index a510d29fb9..178ee6cea5 100644 --- a/src/arch/arm/interrupts.hh +++ b/src/arch/arm/interrupts.hh @@ -133,7 +133,7 @@ class Interrupts : public BaseInterrupts bool checkInterrupts() const override { - HCR hcr = tc->readMiscReg(MISCREG_HCR); + HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); if (!(intStatus || hcr.va || hcr.vi || hcr.vf)) return false; @@ -236,7 +236,7 @@ class Interrupts : public BaseInterrupts { assert(checkInterrupts()); - HCR hcr = tc->readMiscReg(MISCREG_HCR); + HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); bool no_vhe = !HaveExt(tc, ArmExtension::FEAT_VHE); diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 6d9b96d4bc..8813082308 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -796,7 +796,7 @@ ISA::readMiscReg(RegIndex idx) // Security Extensions may limit the readability of CPACR if (release->has(ArmExtension::SECURITY)) { - scr = readMiscRegNoEffect(MISCREG_SCR); + scr = readMiscRegNoEffect(MISCREG_SCR_EL3); cpsr = readMiscRegNoEffect(MISCREG_CPSR); if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); @@ -822,7 +822,7 @@ ISA::readMiscReg(RegIndex idx) case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: cpsr = readMiscRegNoEffect(MISCREG_CPSR); - scr = readMiscRegNoEffect(MISCREG_SCR); + scr = readMiscRegNoEffect(MISCREG_SCR_EL3); if ((cpsr.mode == MODE_HYP) || isSecure(tc)) { return readMiscRegNoEffect(idx); } else { @@ -978,14 +978,6 @@ ISA::readMiscReg(RegIndex idx) case MISCREG_DBGDSCRint: return readMiscRegNoEffect(MISCREG_DBGDSCRint); case MISCREG_ISR: - { - auto ic = dynamic_cast( - tc->getCpuPtr()->getInterruptController(tc->threadId())); - return ic->getISR( - readMiscRegNoEffect(MISCREG_HCR), - readMiscRegNoEffect(MISCREG_CPSR), - readMiscRegNoEffect(MISCREG_SCR)); - } case MISCREG_ISR_EL1: { auto ic = dynamic_cast( @@ -1170,7 +1162,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val) // Security Extensions may limit the writability of CPACR if (release->has(ArmExtension::SECURITY)) { - scr = readMiscRegNoEffect(MISCREG_SCR); + scr = readMiscRegNoEffect(MISCREG_SCR_EL3); CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); @@ -1645,7 +1637,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val) case MISCREG_SCTLR: { DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); - scr = readMiscRegNoEffect(MISCREG_SCR); + scr = readMiscRegNoEffect(MISCREG_SCR_EL3); MiscRegIndex sctlr_idx; if (release->has(ArmExtension::SECURITY) && @@ -2189,7 +2181,7 @@ ISA::addressTranslation(MMU::ArmTranslationType tran_type, if (fault == NoFault) { Addr paddr = req->getPaddr(); TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); - HCR hcr = readMiscRegNoEffect(MISCREG_HCR); + HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2); uint8_t max_paddr_bit = 0; if (release->has(ArmExtension::LPAE) && diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc index 6045c4cd23..824974ab21 100644 --- a/src/arch/arm/mmu.cc +++ b/src/arch/arm/mmu.cc @@ -1316,7 +1316,7 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc, !isSecure)); ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc, !isSecure)); - scr = tc->readMiscReg(MISCREG_SCR); + scr = tc->readMiscReg(MISCREG_SCR_EL3); isPriv = cpsr.mode != MODE_USER; if (longDescFormatInUse(tc)) { uint64_t ttbr_asid = tc->readMiscReg( @@ -1335,7 +1335,7 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc, !isSecure)); dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc, !isSecure)); - hcr = tc->readMiscReg(MISCREG_HCR); + hcr = tc->readMiscReg(MISCREG_HCR_EL2); if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) { vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 6b62e217ff..a534c65fb6 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -669,7 +669,7 @@ AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc) int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) { - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); return snsBankedIndex(reg, tc, scr.ns); } @@ -688,7 +688,7 @@ int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc) { auto *isa = static_cast(tc->getIsaPtr()); - SCR scr = tc->readMiscReg(MISCREG_SCR); + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); return isa->snsBankedIndex64(reg, scr.ns); } diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index e6f4a238a0..f5d37fee8d 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -86,7 +86,7 @@ bool isSecureBelowEL3(ThreadContext *tc) { return ArmSystem::haveEL(tc, EL3) && - static_cast(tc->readMiscRegNoEffect(MISCREG_SCR)).ns == 0; + static_cast(tc->readMiscRegNoEffect(MISCREG_SCR_EL3)).ns == 0; } ExceptionLevel @@ -95,16 +95,10 @@ debugTargetFrom(ThreadContext *tc, bool secure) bool route_to_el2; if (ArmSystem::haveEL(tc, EL2) && (!secure || HaveExt(tc, ArmExtension::FEAT_SEL2))) { - if (ELIs32(tc, EL2)) { - const HCR hcr = tc->readMiscReg(MISCREG_HCR); - const HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); - route_to_el2 = (hdcr.tde == 1 || hcr.tge == 1); - } else { - const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); - const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); - route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1); - } - }else{ + const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); + const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); + route_to_el2 = (mdcr.tde == 1 || hcr.tge == 1); + } else { route_to_el2 = false; } ExceptionLevel target; @@ -239,7 +233,8 @@ s1TranslationRegime(ThreadContext* tc, ExceptionLevel el) if (el != EL0) return el; else if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) && - static_cast(tc->readMiscRegNoEffect(MISCREG_SCR)).ns == 0) + static_cast( + tc->readMiscRegNoEffect(MISCREG_SCR_EL3)).ns == 0) return EL3; else if (HaveExt(tc, ArmExtension::FEAT_VHE) && ELIsInHost(tc, el)) return EL2; @@ -520,7 +515,7 @@ mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, uint32_t opc2; bool trap_to_hyp = false; - const HCR hcr = tc->readMiscReg(MISCREG_HCR); + const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR); const HSTR hstr = tc->readMiscReg(MISCREG_HSTR); const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR); @@ -673,7 +668,7 @@ mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss) uint32_t opc1; uint32_t opc2; - const HCR hcr = tc->readMiscReg(MISCREG_HCR); + const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR); const HSTR hstr = tc->readMiscReg(MISCREG_HSTR); const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR); @@ -740,7 +735,7 @@ mcrrMrrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, bool is_read; bool trap_to_hyp = false; - const HCR hcr = tc->readMiscReg(MISCREG_HCR); + const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); const HSTR hstr = tc->readMiscReg(MISCREG_HSTR); if (EL2Enabled(tc) && (currEL(tc) < EL2)) {