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stats: update for snoop filter tweak

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extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
This commit is contained in:
Curtis Dunham
2016-05-31 11:07:18 +01:00
parent 71a02f624e
commit 62b6ff22ec
184 changed files with 39509 additions and 91985 deletions
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246
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
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@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.869358 # Number of seconds simulated
sim_ticks 1869357988000 # Number of ticks simulated
final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 1869357999000 # Number of ticks simulated
final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1670594 # Simulator instruction rate (inst/s)
host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48045239456 # Simulator tick rate (ticks/s)
host_mem_usage 332628 # Number of bytes of host memory used
host_seconds 38.91 # Real time elapsed on the host
host_inst_rate 1770526 # Simulator instruction rate (inst/s)
host_op_rate 1770526 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50919239991 # Simulator tick rate (ticks/s)
host_mem_usage 331076 # Number of bytes of host memory used
host_seconds 36.71 # Real time elapsed on the host
sim_insts 64999904 # Number of instructions simulated
sim_ops 64999904 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -49,7 +49,7 @@ system.physmem.bw_total::cpu0.data 35592763 # To
system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
@@ -83,7 +83,7 @@ system.cpu0.itb.data_hits 0 # DT
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 3738722771 # number of cpu cycles simulated
system.cpu0.numCycles 3738722793 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
@@ -101,12 +101,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu
system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
@@ -172,7 +172,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
@@ -191,7 +191,7 @@ system.cpu0.num_fp_register_writes 98967 # nu
system.cpu0.num_mem_refs 12536107 # number of memory refs
system.cpu0.num_load_insts 7783754 # Number of load instructions
system.cpu0.num_store_insts 4752353 # Number of store instructions
system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles
system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles
system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles
system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
@@ -231,13 +231,13 @@ system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Cl
system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 49485886 # Class of executed instruction
system.cpu0.dcache.tags.replacements 1781371 # number of replacements
system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks.
system.cpu0.dcache.tags.replacements 1781367 # number of replacements
system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@@ -245,32 +245,32 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits
system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits
system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses
system.cpu0.dcache.demand_hits::cpu0.data 10428970 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 10428970 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10428970 # number of overall hits
system.cpu0.dcache.overall_hits::total 10428970 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses
system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses
system.cpu0.dcache.demand_misses::cpu0.data 1796603 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1796603 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1796603 # number of overall misses
system.cpu0.dcache.overall_misses::total 1796603 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses)
@@ -301,8 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks
system.cpu0.dcache.writebacks::total 633127 # number of writebacks
system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks
system.cpu0.dcache.writebacks::total 633126 # number of writebacks
system.cpu0.icache.tags.replacements 618292 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks.
@@ -383,7 +383,7 @@ system.cpu1.itb.data_hits 0 # DT
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 3738296587 # number of cpu cycles simulated
system.cpu1.numCycles 3738296609 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
@@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu
system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
@@ -457,7 +457,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr
system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
system.cpu1.committedInsts 15522159 # Number of instructions committed
system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed
@@ -474,8 +474,8 @@ system.cpu1.num_fp_register_writes 104129 # nu
system.cpu1.num_mem_refs 4961786 # number of memory refs
system.cpu1.num_load_insts 2849090 # Number of load instructions
system.cpu1.num_store_insts 2112696 # Number of store instructions
system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles
system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles
system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles
system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles
system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
system.cpu1.Branches 2214163 # Number of branches fetched
@@ -515,12 +515,12 @@ system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Cl
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 15525875 # Class of executed instruction
system.cpu1.dcache.tags.replacements 201757 # number of replacements
system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use
system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
@@ -590,7 +590,7 @@ system.cpu1.icache.tags.tagsinuse 453.133719 # Cy
system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy
@@ -679,7 +679,7 @@ system.iocache.tags.tagsinuse 0.434096 # Cy
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit.
system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy
@@ -721,16 +721,16 @@ system.iocache.avg_blocked_cycles::no_targets nan
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.l2c.tags.replacements 999922 # number of replacements
system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use
system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks.
system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use
system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks.
system.l2c.tags.avg_refs 3.999899 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::writebacks 55997.404382 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4860.296070 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4190.275138 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 175.171519 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 114.709600 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy
@@ -744,37 +744,37 @@ system.l2c.tags.age_task_id_blocks_1024::2 6047 #
system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 46377222 # Number of tag accesses
system.l2c.tags.data_accesses 46377222 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits
system.l2c.tags.tag_accesses 46377199 # Number of tag accesses
system.l2c.tags.data_accesses 46377199 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 168081 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 626716 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 129010 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 755726 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 738192 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits
system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 185615 # number of demand (read+write) hits
system.l2c.demand_hits::total 1910407 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits
system.l2c.overall_hits::cpu0.data 738194 # number of overall hits
system.l2c.overall_hits::cpu0.data 738192 # number of overall hits
system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits
system.l2c.overall_hits::cpu1.data 185616 # number of overall hits
system.l2c.overall_hits::total 1910410 # number of overall hits
system.l2c.overall_hits::cpu1.data 185615 # number of overall hits
system.l2c.overall_hits::total 1910407 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses
@@ -800,57 +800,57 @@ system.l2c.overall_misses::cpu0.data 1040486 # nu
system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses
system.l2c.overall_misses::cpu1.data 12101 # number of overall misses
system.l2c.overall_misses::total 1066093 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 777662 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 777662 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 225347 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 293018 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 1553331 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 130045 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1683376 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1778678 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 197716 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2976500 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1778678 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 197716 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2976500 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505314 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.426380 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596534 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.551065 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.584977 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.584977 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses
@@ -862,6 +862,12 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.writebacks::writebacks 80923 # number of writebacks
system.l2c.writebacks::total 80923 # number of writebacks
system.membus.snoop_filter.tot_requests 2182334 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1076327 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
system.membus.trans_dist::ReadResp 948784 # Transaction distribution
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
@@ -871,17 +877,17 @@ system.membus.trans_dist::CleanEvict 918012 # Tr
system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution
system.membus.trans_dist::ReadExReq 125245 # Transaction distribution
system.membus.trans_dist::ReadExReq 125244 # Transaction distribution
system.membus.trans_dist::ReadExResp 124222 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172393 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3216467 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3341628 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes)
@@ -889,61 +895,61 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736
system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2204372 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::samples 2204371 # Request fanout histogram
system.membus.snoop_fanout::mean 0.000517 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.022725 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 2203232 99.95% 99.95% # Request fanout histogram
system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2204372 # Request fanout histogram
system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_fanout::total 2204371 # Request fanout histogram
system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 777662 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1205462 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450127 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 9133705 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766459 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1083516 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram
system.toL2Bus.pkt_size::total 307065106 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1000943 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 7058663 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.106768 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 6305567 89.33% 89.33% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 752556 10.66% 99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

10
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
sim_ticks 1829331993500 # Number of ticks simulated
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1840131 # Simulator instruction rate (inst/s)
host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56067507873 # Simulator tick rate (ticks/s)
host_mem_usage 330836 # Number of bytes of host memory used
host_seconds 32.63 # Real time elapsed on the host
host_inst_rate 1838030 # Simulator instruction rate (inst/s)
host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56003449171 # Simulator tick rate (ticks/s)
host_mem_usage 325188 # Number of bytes of host memory used
host_seconds 32.66 # Real time elapsed on the host
sim_insts 60038469 # Number of instructions simulated
sim_ops 60038469 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

2777
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

10
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu
sim_ticks 1941275996000 # Number of ticks simulated
final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1048317 # Simulator instruction rate (inst/s)
host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36222399744 # Simulator tick rate (ticks/s)
host_mem_usage 330588 # Number of bytes of host memory used
host_seconds 53.59 # Real time elapsed on the host
host_inst_rate 855166 # Simulator instruction rate (inst/s)
host_op_rate 855166 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29548473540 # Simulator tick rate (ticks/s)
host_mem_usage 325188 # Number of bytes of host memory used
host_seconds 65.70 # Real time elapsed on the host
sim_insts 56182685 # Number of instructions simulated
sim_ops 56182685 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
sim_ticks 2783854535000 # Number of ticks simulated
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1211130 # Simulator instruction rate (inst/s)
host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23615387886 # Simulator tick rate (ticks/s)
host_mem_usage 581436 # Number of bytes of host memory used
host_seconds 117.88 # Real time elapsed on the host
host_inst_rate 1008697 # Simulator instruction rate (inst/s)
host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19668230366 # Simulator tick rate (ticks/s)
host_mem_usage 576064 # Number of bytes of host memory used
host_seconds 141.54 # Real time elapsed on the host
sim_insts 142771651 # Number of instructions simulated
sim_ops 173801592 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

1407
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

10
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
sim_ticks 2783854535000 # Number of ticks simulated
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1225194 # Simulator instruction rate (inst/s)
host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23889629831 # Simulator tick rate (ticks/s)
host_mem_usage 578692 # Number of bytes of host memory used
host_seconds 116.53 # Real time elapsed on the host
host_inst_rate 888036 # Simulator instruction rate (inst/s)
host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17315504636 # Simulator tick rate (ticks/s)
host_mem_usage 573724 # Number of bytes of host memory used
host_seconds 160.77 # Real time elapsed on the host
sim_insts 142771651 # Number of instructions simulated
sim_ops 173801592 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

4788
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

10
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu
sim_ticks 2909586837500 # Number of ticks simulated
final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 812558 # Simulator instruction rate (inst/s)
host_op_rate 979692 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21023218607 # Simulator tick rate (ticks/s)
host_mem_usage 578440 # Number of bytes of host memory used
host_seconds 138.40 # Real time elapsed on the host
host_inst_rate 581636 # Simulator instruction rate (inst/s)
host_op_rate 701272 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15048595995 # Simulator tick rate (ticks/s)
host_mem_usage 573724 # Number of bytes of host memory used
host_seconds 193.35 # Real time elapsed on the host
sim_insts 112457033 # Number of instructions simulated
sim_ops 135588117 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

836
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
View File

File diff suppressed because it is too large Load Diff

2948
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

10
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu
sim_ticks 5112151729000 # Number of ticks simulated
final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1369712 # Simulator instruction rate (inst/s)
host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34999130987 # Simulator tick rate (ticks/s)
host_mem_usage 614748 # Number of bytes of host memory used
host_seconds 146.07 # Real time elapsed on the host
host_inst_rate 1314225 # Simulator instruction rate (inst/s)
host_op_rate 2690507 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33581335470 # Simulator tick rate (ticks/s)
host_mem_usage 609616 # Number of bytes of host memory used
host_seconds 152.23 # Real time elapsed on the host
sim_insts 200067055 # Number of instructions simulated
sim_ops 409581065 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 5.194946 # Nu
sim_ticks 5194946000500 # Number of ticks simulated
final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 910377 # Simulator instruction rate (inst/s)
host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36822413305 # Simulator tick rate (ticks/s)
host_mem_usage 616280 # Number of bytes of host memory used
host_seconds 141.08 # Real time elapsed on the host
host_inst_rate 930999 # Simulator instruction rate (inst/s)
host_op_rate 1794485 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37656529565 # Simulator tick rate (ticks/s)
host_mem_usage 609616 # Number of bytes of host memory used
host_seconds 137.96 # Real time elapsed on the host
sim_insts 128436892 # Number of instructions simulated
sim_ops 247560077 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

20
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
sim_ticks 200409271000 # Number of ticks simulated
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 7747436 # Simulator instruction rate (inst/s)
host_op_rate 7747432 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2964324473 # Simulator tick rate (ticks/s)
host_mem_usage 475456 # Number of bytes of host memory used
host_seconds 67.61 # Real time elapsed on the host
host_inst_rate 17114164 # Simulator instruction rate (inst/s)
host_op_rate 17114158 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6548224120 # Simulator tick rate (ticks/s)
host_mem_usage 490760 # Number of bytes of host memory used
host_seconds 30.61 # Real time elapsed on the host
sim_insts 523780905 # Number of instructions simulated
sim_ops 523780905 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
@@ -619,11 +619,11 @@ sim_seconds 0.000407 # Nu
sim_ticks 407341500 # Number of ticks simulated
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3441354505 # Simulator instruction rate (inst/s)
host_op_rate 3440623178 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2674872126 # Simulator tick rate (ticks/s)
host_mem_usage 475456 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_inst_rate 9054438128 # Simulator instruction rate (inst/s)
host_op_rate 9052667837 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7037972394 # Simulator tick rate (ticks/s)
host_mem_usage 490760 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 523853183 # Number of instructions simulated
sim_ops 523853183 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000037 # Nu
sim_ticks 37494000 # Number of ticks simulated
final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 141195 # Simulator instruction rate (inst/s)
host_op_rate 141164 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 825166364 # Simulator tick rate (ticks/s)
host_mem_usage 252900 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 176621 # Simulator instruction rate (inst/s)
host_op_rate 176529 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1031613588 # Simulator tick rate (ticks/s)
host_mem_usage 248004 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 6413 # Number of instructions simulated
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
sim_ticks 22019000 # Number of ticks simulated
final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 140516 # Simulator instruction rate (inst/s)
host_op_rate 140486 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 484379589 # Simulator tick rate (ticks/s)
host_mem_usage 253664 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 115969 # Simulator instruction rate (inst/s)
host_op_rate 115940 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 399737091 # Simulator tick rate (ticks/s)
host_mem_usage 249288 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 6385 # Number of instructions simulated
sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 3214500 # Number of ticks simulated
final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 21023 # Simulator instruction rate (inst/s)
host_op_rate 21020 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10551583 # Simulator tick rate (ticks/s)
host_mem_usage 216888 # Number of bytes of host memory used
host_seconds 0.30 # Real time elapsed on the host
host_inst_rate 1011674 # Simulator instruction rate (inst/s)
host_op_rate 1009913 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 506215370 # Simulator tick rate (ticks/s)
host_mem_usage 237756 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu
sim_ticks 121535 # Number of ticks simulated
final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 23854 # Simulator instruction rate (inst/s)
host_op_rate 23852 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 452710 # Simulator tick rate (ticks/s)
host_mem_usage 387364 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
host_inst_rate 71837 # Simulator instruction rate (inst/s)
host_op_rate 71828 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1363198 # Simulator tick rate (ticks/s)
host_mem_usage 407704 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu
sim_ticks 108878 # Number of ticks simulated
final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 17471 # Simulator instruction rate (inst/s)
host_op_rate 17470 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 297052 # Simulator tick rate (ticks/s)
host_mem_usage 393472 # Number of bytes of host memory used
host_seconds 0.37 # Real time elapsed on the host
host_inst_rate 68389 # Simulator instruction rate (inst/s)
host_op_rate 68380 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1162621 # Simulator tick rate (ticks/s)
host_mem_usage 413676 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu
sim_ticks 108253 # Number of ticks simulated
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 39556 # Simulator instruction rate (inst/s)
host_op_rate 39552 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 668635 # Simulator tick rate (ticks/s)
host_mem_usage 388512 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
host_inst_rate 4411 # Simulator instruction rate (inst/s)
host_op_rate 4411 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 74577 # Simulator tick rate (ticks/s)
host_mem_usage 409256 # Number of bytes of host memory used
host_seconds 1.45 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu
sim_ticks 86770 # Number of ticks simulated
final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 43915 # Simulator instruction rate (inst/s)
host_op_rate 43910 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 594975 # Simulator tick rate (ticks/s)
host_mem_usage 388108 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_inst_rate 99240 # Simulator instruction rate (inst/s)
host_op_rate 99218 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1344283 # Simulator tick rate (ticks/s)
host_mem_usage 407932 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu
sim_ticks 107065 # Number of ticks simulated
final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 18652 # Simulator instruction rate (inst/s)
host_op_rate 18652 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 311861 # Simulator tick rate (ticks/s)
host_mem_usage 390536 # Number of bytes of host memory used
host_seconds 0.34 # Real time elapsed on the host
host_inst_rate 109103 # Simulator instruction rate (inst/s)
host_op_rate 109072 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1823360 # Simulator tick rate (ticks/s)
host_mem_usage 411068 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu
sim_ticks 35682500 # Number of ticks simulated
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 421865 # Simulator instruction rate (inst/s)
host_op_rate 421312 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2345119890 # Simulator tick rate (ticks/s)
host_mem_usage 251096 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_inst_rate 581025 # Simulator instruction rate (inst/s)
host_op_rate 580437 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3231677275 # Simulator tick rate (ticks/s)
host_mem_usage 247496 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
sim_ticks 20320000 # Number of ticks simulated
final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 183657 # Simulator instruction rate (inst/s)
host_op_rate 183501 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1441333472 # Simulator tick rate (ticks/s)
host_mem_usage 251592 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_inst_rate 154508 # Simulator instruction rate (inst/s)
host_op_rate 154391 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1212791416 # Simulator tick rate (ticks/s)
host_mem_usage 246696 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
sim_ticks 12409500 # Number of ticks simulated
final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 67215 # Simulator instruction rate (inst/s)
host_op_rate 67181 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 349098234 # Simulator tick rate (ticks/s)
host_mem_usage 252356 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_inst_rate 87055 # Simulator instruction rate (inst/s)
host_op_rate 87008 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 452104980 # Simulator tick rate (ticks/s)
host_mem_usage 247976 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54662 # Simulator instruction rate (inst/s)
host_op_rate 54627 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27487977 # Simulator tick rate (ticks/s)
host_mem_usage 219680 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 461545 # Simulator instruction rate (inst/s)
host_op_rate 460635 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 231518490 # Simulator tick rate (ticks/s)
host_mem_usage 237472 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000046 # Nu
sim_ticks 45733 # Number of ticks simulated
final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 42490 # Simulator instruction rate (inst/s)
host_op_rate 42477 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 753627 # Simulator tick rate (ticks/s)
host_mem_usage 411088 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_inst_rate 63739 # Simulator instruction rate (inst/s)
host_op_rate 63721 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1130531 # Simulator tick rate (ticks/s)
host_mem_usage 407420 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu
sim_ticks 41712 # Number of ticks simulated
final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 38081 # Simulator instruction rate (inst/s)
host_op_rate 38070 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 616024 # Simulator tick rate (ticks/s)
host_mem_usage 414508 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_inst_rate 64355 # Simulator instruction rate (inst/s)
host_op_rate 64336 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1041083 # Simulator tick rate (ticks/s)
host_mem_usage 410320 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu
sim_ticks 40527 # Number of ticks simulated
final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 25710 # Simulator instruction rate (inst/s)
host_op_rate 25704 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 404148 # Simulator tick rate (ticks/s)
host_mem_usage 390780 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 1955 # Simulator instruction rate (inst/s)
host_op_rate 1955 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 30751 # Simulator tick rate (ticks/s)
host_mem_usage 407948 # Number of bytes of host memory used
host_seconds 1.32 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
sim_ticks 32936 # Number of ticks simulated
final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 52774 # Simulator instruction rate (inst/s)
host_op_rate 52753 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 673978 # Simulator tick rate (ticks/s)
host_mem_usage 411572 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 83066 # Simulator instruction rate (inst/s)
host_op_rate 82987 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1059779 # Simulator tick rate (ticks/s)
host_mem_usage 407644 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu
sim_ticks 41659 # Number of ticks simulated
final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 41992 # Simulator instruction rate (inst/s)
host_op_rate 41979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 678429 # Simulator tick rate (ticks/s)
host_mem_usage 412928 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_inst_rate 92225 # Simulator instruction rate (inst/s)
host_op_rate 92177 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1489374 # Simulator tick rate (ticks/s)
host_mem_usage 407716 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000018 # Nu
sim_ticks 18239500 # Number of ticks simulated
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 277034 # Simulator instruction rate (inst/s)
host_op_rate 276552 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1954350939 # Simulator tick rate (ticks/s)
host_mem_usage 249792 # Number of bytes of host memory used
host_inst_rate 339288 # Simulator instruction rate (inst/s)
host_op_rate 338780 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2394585777 # Simulator tick rate (ticks/s)
host_mem_usage 246188 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated

10
tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu
sim_ticks 29977500 # Number of ticks simulated
final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 89930 # Simulator instruction rate (inst/s)
host_op_rate 105235 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 584953104 # Simulator tick rate (ticks/s)
host_mem_usage 268772 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 146522 # Simulator instruction rate (inst/s)
host_op_rate 171470 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 953185288 # Simulator tick rate (ticks/s)
host_mem_usage 264656 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 4605 # Number of instructions simulated
sim_ops 5391 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
sim_ticks 17232500 # Number of ticks simulated
final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 43939 # Simulator instruction rate (inst/s)
host_op_rate 51450 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 164826819 # Simulator tick rate (ticks/s)
host_mem_usage 269540 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 66942 # Simulator instruction rate (inst/s)
host_op_rate 78386 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 251130115 # Simulator tick rate (ticks/s)
host_mem_usage 265932 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
sim_ticks 18821000 # Number of ticks simulated
final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 49791 # Simulator instruction rate (inst/s)
host_op_rate 58299 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 203978556 # Simulator tick rate (ticks/s)
host_mem_usage 266084 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_inst_rate 45352 # Simulator instruction rate (inst/s)
host_op_rate 53108 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 185838458 # Simulator tick rate (ticks/s)
host_mem_usage 261708 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 13445 # Simulator instruction rate (inst/s)
host_op_rate 15745 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7889483 # Simulator tick rate (ticks/s)
host_mem_usage 237392 # Number of bytes of host memory used
host_seconds 0.34 # Real time elapsed on the host
host_inst_rate 274500 # Simulator instruction rate (inst/s)
host_op_rate 321069 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 160714630 # Simulator tick rate (ticks/s)
host_mem_usage 254660 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 30076 # Simulator instruction rate (inst/s)
host_op_rate 35217 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17644392 # Simulator tick rate (ticks/s)
host_mem_usage 236884 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_inst_rate 363981 # Simulator instruction rate (inst/s)
host_op_rate 425522 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 212904964 # Simulator tick rate (ticks/s)
host_mem_usage 254404 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu
sim_ticks 28298500 # Number of ticks simulated
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 441317 # Simulator instruction rate (inst/s)
host_op_rate 514292 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2726097982 # Simulator tick rate (ticks/s)
host_mem_usage 267744 # Number of bytes of host memory used
host_inst_rate 343617 # Simulator instruction rate (inst/s)
host_op_rate 400476 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2123290642 # Simulator tick rate (ticks/s)
host_mem_usage 263372 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4566 # Number of instructions simulated
sim_ops 5330 # Number of ops (including micro ops) simulated

10
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu
sim_ticks 22532000 # Number of ticks simulated
final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 65525 # Simulator instruction rate (inst/s)
host_op_rate 65509 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 295199371 # Simulator tick rate (ticks/s)
host_mem_usage 251356 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_inst_rate 96442 # Simulator instruction rate (inst/s)
host_op_rate 96403 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 434426491 # Simulator tick rate (ticks/s)
host_mem_usage 247240 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 4999 # Number of instructions simulated
sim_ops 4999 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2820500 # Number of ticks simulated
final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 42403 # Simulator instruction rate (inst/s)
host_op_rate 42398 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21196256 # Simulator tick rate (ticks/s)
host_mem_usage 214708 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_inst_rate 876414 # Simulator instruction rate (inst/s)
host_op_rate 873362 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 435104956 # Simulator tick rate (ticks/s)
host_mem_usage 235716 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000100 # Nu
sim_ticks 100232 # Number of ticks simulated
final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 20831 # Simulator instruction rate (inst/s)
host_op_rate 20830 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 370097 # Simulator tick rate (ticks/s)
host_mem_usage 389556 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
host_inst_rate 97717 # Simulator instruction rate (inst/s)
host_op_rate 97699 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1735645 # Simulator tick rate (ticks/s)
host_mem_usage 410048 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000034 # Nu
sim_ticks 33932500 # Number of ticks simulated
final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 442497 # Simulator instruction rate (inst/s)
host_op_rate 441783 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2653552582 # Simulator tick rate (ticks/s)
host_mem_usage 249064 # Number of bytes of host memory used
host_inst_rate 431758 # Simulator instruction rate (inst/s)
host_op_rate 430982 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2588300068 # Simulator tick rate (ticks/s)
host_mem_usage 244424 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated

10
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
sim_ticks 19908000 # Number of ticks simulated
final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 130311 # Simulator instruction rate (inst/s)
host_op_rate 130281 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 447700777 # Simulator tick rate (ticks/s)
host_mem_usage 249300 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_inst_rate 120043 # Simulator instruction rate (inst/s)
host_op_rate 120013 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 412413617 # Simulator tick rate (ticks/s)
host_mem_usage 245176 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 76704 # Simulator instruction rate (inst/s)
host_op_rate 76683 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38324639 # Simulator tick rate (ticks/s)
host_mem_usage 216536 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_inst_rate 887311 # Simulator instruction rate (inst/s)
host_op_rate 885785 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 442112700 # Simulator tick rate (ticks/s)
host_mem_usage 234416 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 62253 # Simulator instruction rate (inst/s)
host_op_rate 62235 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31469743 # Simulator tick rate (ticks/s)
host_mem_usage 218904 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_inst_rate 633206 # Simulator instruction rate (inst/s)
host_op_rate 631372 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 318532177 # Simulator tick rate (ticks/s)
host_mem_usage 236156 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000082 # Nu
sim_ticks 81703 # Number of ticks simulated
final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 27831 # Simulator instruction rate (inst/s)
host_op_rate 27828 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 426765 # Simulator tick rate (ticks/s)
host_mem_usage 393224 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_inst_rate 79389 # Simulator instruction rate (inst/s)
host_op_rate 79372 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1217125 # Simulator tick rate (ticks/s)
host_mem_usage 409468 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000031 # Nu
sim_ticks 30526500 # Number of ticks simulated
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 608531 # Simulator instruction rate (inst/s)
host_op_rate 607803 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3479427932 # Simulator tick rate (ticks/s)
host_mem_usage 249516 # Number of bytes of host memory used
host_inst_rate 398653 # Simulator instruction rate (inst/s)
host_op_rate 397863 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2276293986 # Simulator tick rate (ticks/s)
host_mem_usage 245124 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated

10
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
sim_ticks 21273500 # Number of ticks simulated
final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 70008 # Simulator instruction rate (inst/s)
host_op_rate 126817 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 276755373 # Simulator tick rate (ticks/s)
host_mem_usage 271684 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_inst_rate 54566 # Simulator instruction rate (inst/s)
host_op_rate 98846 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 215714601 # Simulator tick rate (ticks/s)
host_mem_usage 266040 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 26569 # Simulator instruction rate (inst/s)
host_op_rate 48126 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27718570 # Simulator tick rate (ticks/s)
host_mem_usage 237032 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
host_inst_rate 380560 # Simulator instruction rate (inst/s)
host_op_rate 688269 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 395838528 # Simulator tick rate (ticks/s)
host_mem_usage 254256 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
sim_ticks 87948 # Number of ticks simulated
final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 28860 # Simulator instruction rate (inst/s)
host_op_rate 52275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 471584 # Simulator tick rate (ticks/s)
host_mem_usage 411784 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_inst_rate 77426 # Simulator instruction rate (inst/s)
host_op_rate 140230 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1264887 # Simulator tick rate (ticks/s)
host_mem_usage 428592 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000031 # Nu
sim_ticks 30886500 # Number of ticks simulated
final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 235920 # Simulator instruction rate (inst/s)
host_op_rate 427054 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1352150005 # Simulator tick rate (ticks/s)
host_mem_usage 266824 # Number of bytes of host memory used
host_inst_rate 324268 # Simulator instruction rate (inst/s)
host_op_rate 586988 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1858658321 # Simulator tick rate (ticks/s)
host_mem_usage 262968 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated

10
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu
sim_ticks 25580500 # Number of ticks simulated
final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 85448 # Simulator instruction rate (inst/s)
host_op_rate 85436 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 171120344 # Simulator tick rate (ticks/s)
host_mem_usage 253996 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_inst_rate 119260 # Simulator instruction rate (inst/s)
host_op_rate 119247 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 238851205 # Simulator tick rate (ticks/s)
host_mem_usage 249876 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 12770 # Number of instructions simulated
sim_ops 12770 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

947
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View File

@@ -1,947 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000029 # Number of seconds simulated
sim_ticks 28845500 # Number of ticks simulated
final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 68981 # Simulator instruction rate (inst/s)
host_op_rate 68975 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 137812851 # Simulator tick rate (ticks/s)
host_mem_usage 251992 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 510 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 511 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 105 # Per bank write bursts
system.physmem.perBankRdBursts::1 28 # Per bank write bursts
system.physmem.perBankRdBursts::2 53 # Per bank write bursts
system.physmem.perBankRdBursts::3 27 # Per bank write bursts
system.physmem.perBankRdBursts::4 23 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 38 # Per bank write bursts
system.physmem.perBankRdBursts::8 7 # Per bank write bursts
system.physmem.perBankRdBursts::9 4 # Per bank write bursts
system.physmem.perBankRdBursts::10 2 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 57 # Per bank write bursts
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankRdBursts::14 63 # Per bank write bursts
system.physmem.perBankRdBursts::15 41 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 28814000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 511 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation
system.physmem.totQLat 3584250 # Total ticks spent queuing
system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 8.86 # Data bus utilization in percentage
system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 428 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 56387.48 # Average gap between requests
system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 12618 # Number of BP lookups
system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups
system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 57692 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 796 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 25362 # Type of FU issued
system.cpu.iq.rate 0.439610 # Inst issue rate
system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1579 # number of nop insts executed
system.cpu.iew.exec_refs 6244 # number of memory reference insts executed
system.cpu.iew.exec_branches 5021 # Number of branches executed
system.cpu.iew.exec_stores 2299 # Number of stores executed
system.cpu.iew.exec_rate 0.411045 # Inst execution rate
system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10530 # num instructions producing a value
system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3673 # Number of memory references committed
system.cpu.commit.loads 2225 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3358 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 62581 # The number of ROB reads
system.cpu.rob.rob_writes 65380 # The number of ROB writes
system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 36850 # number of integer regfile reads
system.cpu.int_regfile_writes 20548 # number of integer regfile writes
system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits
system.cpu.dcache.overall_hits::total 4642 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses
system.cpu.dcache.overall_misses::total 549 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses
system.cpu.icache.tags.data_accesses 15425 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits
system.cpu.icache.overall_hits::total 6949 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses
system.cpu.icache.overall_misses::total 581 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
system.cpu.l2cache.overall_misses::total 511 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadResp 426 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 511 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 511 # Request fanout histogram
system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 9.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

124
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
View File

@@ -1,124 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000008 # Number of seconds simulated
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 20450 # Simulator instruction rate (inst/s)
host_op_rate 20449 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10266040 # Simulator tick rate (ticks/s)
host_mem_usage 218684 # Number of bytes of host memory used
host_seconds 0.74 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory
system.physmem.bytes_read::total 72170 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory
system.physmem.bytes_written::total 9042 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory
system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory
system.physmem.num_other::total 6 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15225 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 15162 # Number of instructions committed
system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
system.cpu.num_int_insts 12219 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
system.cpu.num_int_register_writes 13819 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 3683 # number of memory refs
system.cpu.num_load_insts 2231 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 3363 # Number of branches fetched
system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
system.membus.trans_dist::ReadReq 17432 # Transaction distribution
system.membus.trans_dist::ReadResp 17432 # Transaction distribution
system.membus.trans_dist::WriteReq 1442 # Transaction distribution
system.membus.trans_dist::WriteResp 1442 # Transaction distribution
system.membus.trans_dist::SwapReq 6 # Transaction distribution
system.membus.trans_dist::SwapResp 6 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 18880 # Request fanout histogram
system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram
system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 18880 # Request fanout histogram
---------- End Simulation Statistics ----------

474
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
View File

@@ -1,474 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000044 # Number of seconds simulated
sim_ticks 44282500 # Number of ticks simulated
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 298703 # Simulator instruction rate (inst/s)
host_op_rate 298583 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 871748609 # Simulator tick rate (ticks/s)
host_mem_usage 249440 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 88565 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 15162 # Number of instructions committed
system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
system.cpu.num_int_insts 12219 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 3683 # number of memory refs
system.cpu.num_load_insts 2231 # Number of load instructions
system.cpu.num_store_insts 1452 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 3363 # Number of branches fetched
system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
system.cpu.dcache.overall_hits::total 3529 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.dcache.overall_misses::total 138 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
system.cpu.icache.overall_hits::total 14928 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
system.cpu.icache.overall_misses::total 280 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 416 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 331 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 416 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 416 # Request fanout histogram
system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 4.7 # Layer utilization (%)
---------- End Simulation Statistics ----------

10
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000405 # Nu
sim_ticks 405365000 # Number of ticks simulated
final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 83628 # Simulator instruction rate (inst/s)
host_op_rate 83610 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5251060650 # Simulator tick rate (ticks/s)
host_mem_usage 610048 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_inst_rate 217578 # Simulator instruction rate (inst/s)
host_op_rate 217432 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 13650898473 # Simulator tick rate (ticks/s)
host_mem_usage 630716 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 6453 # Number of instructions simulated
sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000061 # Nu
sim_ticks 61470000 # Number of ticks simulated
final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 583425 # Simulator instruction rate (inst/s)
host_op_rate 580281 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5518802940 # Simulator tick rate (ticks/s)
host_mem_usage 637904 # Number of bytes of host memory used
host_inst_rate 556042 # Simulator instruction rate (inst/s)
host_op_rate 555477 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5286056763 # Simulator tick rate (ticks/s)
host_mem_usage 634812 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6453 # Number of instructions simulated
sim_ops 6453 # Number of ops (including micro ops) simulated

10
tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000326 # Nu
sim_ticks 325849000 # Number of ticks simulated
final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 67062 # Simulator instruction rate (inst/s)
host_op_rate 77548 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4377845869 # Simulator tick rate (ticks/s)
host_mem_usage 629736 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_inst_rate 156546 # Simulator instruction rate (inst/s)
host_op_rate 180975 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10214317316 # Simulator tick rate (ticks/s)
host_mem_usage 647364 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 4988 # Number of instructions simulated
sim_ops 5770 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu
sim_ticks 49855000 # Number of ticks simulated
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 523400 # Simulator instruction rate (inst/s)
host_op_rate 604831 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5220928914 # Simulator tick rate (ticks/s)
host_mem_usage 655332 # Number of bytes of host memory used
host_inst_rate 388067 # Simulator instruction rate (inst/s)
host_op_rate 448196 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3866626926 # Simulator tick rate (ticks/s)
host_mem_usage 651460 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4988 # Number of instructions simulated
sim_ops 5770 # Number of ops (including micro ops) simulated

10
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000369 # Nu
sim_ticks 368887000 # Number of ticks simulated
final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 25687 # Simulator instruction rate (inst/s)
host_op_rate 25686 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1679592961 # Simulator tick rate (ticks/s)
host_mem_usage 607900 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
host_inst_rate 294016 # Simulator instruction rate (inst/s)
host_op_rate 293668 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19182713753 # Simulator tick rate (ticks/s)
host_mem_usage 628676 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000059 # Nu
sim_ticks 58892000 # Number of ticks simulated
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 350541 # Simulator instruction rate (inst/s)
host_op_rate 350101 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3650563038 # Simulator tick rate (ticks/s)
host_mem_usage 636120 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_inst_rate 509573 # Simulator instruction rate (inst/s)
host_op_rate 509069 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5309891860 # Simulator tick rate (ticks/s)
host_mem_usage 632772 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts

10
tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000333 # Nu
sim_ticks 333033000 # Number of ticks simulated
final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 75807 # Simulator instruction rate (inst/s)
host_op_rate 75776 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4546866876 # Simulator tick rate (ticks/s)
host_mem_usage 611808 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_inst_rate 348800 # Simulator instruction rate (inst/s)
host_op_rate 348537 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20908249754 # Simulator tick rate (ticks/s)
host_mem_usage 629116 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5548 # Number of instructions simulated
sim_ops 5548 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000053 # Nu
sim_ticks 53334000 # Number of ticks simulated
final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 388058 # Simulator instruction rate (inst/s)
host_op_rate 387570 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3721714769 # Simulator tick rate (ticks/s)
host_mem_usage 636836 # Number of bytes of host memory used
host_inst_rate 429905 # Simulator instruction rate (inst/s)
host_op_rate 429380 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4122052129 # Simulator tick rate (ticks/s)
host_mem_usage 633208 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5548 # Number of instructions simulated
sim_ops 5548 # Number of ops (including micro ops) simulated

10
tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000445 # Nu
sim_ticks 445082000 # Number of ticks simulated
final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66069 # Simulator instruction rate (inst/s)
host_op_rate 119271 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5145784728 # Simulator tick rate (ticks/s)
host_mem_usage 629884 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_inst_rate 211115 # Simulator instruction rate (inst/s)
host_op_rate 380995 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16432986499 # Simulator tick rate (ticks/s)
host_mem_usage 647212 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 5712 # Number of instructions simulated
sim_ops 10314 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts

8
tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
View File

@@ -4,10 +4,10 @@ sim_seconds 0.000056 # Nu
sim_ticks 55844000 # Number of ticks simulated
final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 250477 # Simulator instruction rate (inst/s)
host_op_rate 451948 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2445398371 # Simulator tick rate (ticks/s)
host_mem_usage 655164 # Number of bytes of host memory used
host_inst_rate 299396 # Simulator instruction rate (inst/s)
host_op_rate 540174 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2922543083 # Simulator tick rate (ticks/s)
host_mem_usage 651308 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5712 # Number of instructions simulated
sim_ops 10314 # Number of ops (including micro ops) simulated

10
tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.000663 # Nu
sim_ticks 663454500 # Number of ticks simulated
final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 97803 # Simulator instruction rate (inst/s)
host_op_rate 201121 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 968968514 # Simulator tick rate (ticks/s)
host_mem_usage 1290208 # Number of bytes of host memory used
host_seconds 0.68 # Real time elapsed on the host
host_inst_rate 153021 # Simulator instruction rate (inst/s)
host_op_rate 314663 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1515963159 # Simulator tick rate (ticks/s)
host_mem_usage 1308268 # Number of bytes of host memory used
host_seconds 0.44 # Real time elapsed on the host
sim_insts 66963 # Number of instructions simulated
sim_ops 137705 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts

243
tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -1,243 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.054141 # Number of seconds simulated
sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 763855 # Simulator instruction rate (inst/s)
host_op_rate 767659 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 456454296 # Simulator tick rate (ticks/s)
host_mem_usage 371948 # Number of bytes of host memory used
host_seconds 118.61 # Real time elapsed on the host
sim_insts 90602408 # Number of instructions simulated
sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 108282002 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602408 # Number of instructions committed
system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
system.cpu.num_int_insts 72326352 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732305 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054081 # Class of executed instruction
system.membus.trans_dist::ReadReq 130287906 # Transaction distribution
system.membus.trans_dist::ReadResp 130291793 # Transaction distribution
system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram
system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 135031171 # Request fanout histogram
---------- End Simulation Statistics ----------

648
tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View File

@@ -1,648 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.147149 # Number of seconds simulated
sim_ticks 147148719500 # Number of ticks simulated
final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1067474 # Simulator instruction rate (inst/s)
host_op_rate 1072778 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1734188097 # Simulator tick rate (ticks/s)
host_mem_usage 402040 # Number of bytes of host memory used
host_seconds 84.85 # Real time elapsed on the host
sim_insts 90576862 # Number of instructions simulated
sim_ops 91026991 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 294297439 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576862 # Number of instructions committed
system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
system.cpu.num_int_insts 72326352 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732305 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054081 # Class of executed instruction
system.cpu.dcache.tags.replacements 942702 # number of replacements
system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits
system.cpu.dcache.overall_hits::total 26245827 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
system.cpu.dcache.overall_misses::total 946799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
system.cpu.dcache.writebacks::total 942334 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
system.cpu.icache.tags.replacements 2 # number of replacements
system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
system.cpu.icache.overall_hits::total 107830173 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 2 # number of writebacks
system.cpu.icache.writebacks::total 2 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits
system.cpu.l2cache.overall_hits::total 932057 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 792 # Transaction distribution
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15340 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15340 # Request fanout histogram
system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

124
tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View File

@@ -1,124 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.122216 # Number of seconds simulated
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1145191 # Simulator instruction rate (inst/s)
host_op_rate 1145238 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 574019671 # Simulator tick rate (ticks/s)
host_mem_usage 353116 # Number of bytes of host memory used
host_seconds 212.91 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory
system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431648 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29302884 # Number of branches fetched
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
system.membus.trans_dist::SwapReq 3886 # Transaction distribution
system.membus.trans_dist::SwapResp 3886 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 349547768 # Request fanout histogram
---------- End Simulation Statistics ----------

127
tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View File

@@ -1,127 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 537919 # Simulator instruction rate (inst/s)
host_op_rate 947189 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 575240737 # Simulator tick rate (ticks/s)
host_mem_usage 379572 # Number of bytes of host memory used
host_seconds 293.70 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900081 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 8475189 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278169482 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
system.cpu.num_mem_refs 122219137 # number of memory refs
system.cpu.num_load_insts 90779385 # Number of load instructions
system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29309705 # Number of branches fetched
system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram
system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 339915363 # Request fanout histogram
---------- End Simulation Statistics ----------

152
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View File

@@ -1,152 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1181428 # Simulator instruction rate (inst/s)
host_op_rate 1181354 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 590676886 # Simulator tick rate (ticks/s)
host_mem_usage 220296 # Number of bytes of host memory used
host_seconds 0.42 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory
system.physmem.bytes_written::total 417562 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory
system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory
system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.itb.fetch_hits 500019 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 500032 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 500032 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu.num_func_calls 14357 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu.num_int_insts 474689 # number of integer instructions
system.cpu.num_fp_insts 32 # number of float instructions
system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 180793 # number of memory refs
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 500032 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 59023 # Number of branches fetched
system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
system.membus.trans_dist::ReadReq 624454 # Transaction distribution
system.membus.trans_dist::ReadResp 624454 # Transaction distribution
system.membus.trans_dist::WriteReq 56340 # Transaction distribution
system.membus.trans_dist::WriteResp 56340 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 680794 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 680794 # Request fanout histogram
---------- End Simulation Statistics ----------

497
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View File

@@ -1,497 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000733 # Number of seconds simulated
sim_ticks 733071500 # Number of ticks simulated
final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 558953 # Simulator instruction rate (inst/s)
host_op_rate 558933 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 819448941 # Simulator tick rate (ticks/s)
host_mem_usage 229836 # Number of bytes of host memory used
host_seconds 0.89 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 35183471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39635970 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 74819441 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 35183471 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 35183471 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.itb.fetch_hits 500020 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 500033 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 1466143 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu.num_func_calls 14357 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu.num_int_insts 474689 # number of integer instructions
system.cpu.num_fp_insts 32 # number of float instructions
system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 180793 # number of memory refs
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1466143 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 59023 # Number of branches fetched
system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 286.668758 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.069987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.069987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
system.cpu.dcache.overall_hits::total 180321 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.dcache.overall_misses::total 454 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19530000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 19530000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8618000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8618000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28148000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28148000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28148000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28148000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19215000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19215000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8479000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8479000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27694000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 27694000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27694000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 27694000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 264.585152 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.129192 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.129192 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits
system.cpu.icache.overall_hits::total 499617 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.icache.overall_misses::total 403 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24986500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24986500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24986500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24986500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24986500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24986500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62001.240695 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62001.240695 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62001.240695 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62001.240695 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24583500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 24583500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24583500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 24583500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24583500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 24583500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61001.240695 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61001.240695 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 264.590924 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.089673 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008075 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006595 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.014669 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 718 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses
system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 403 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 315 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 315 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8270500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23979000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 23979000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18742500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18742500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 23979000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 27013000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 50992000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 23979000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 27013000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 50992000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 403 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 403 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 315 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.240695 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.240695 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.583431 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.583431 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 403 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 315 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 315 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6880500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6880500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19949000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19949000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15592500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15592500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19949000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22473000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 42422000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19949000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22473000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 42422000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 857 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 718 # Transaction distribution
system.membus.trans_dist::ReadExReq 139 # Transaction distribution
system.membus.trans_dist::ReadExResp 139 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 857 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 857 # Request fanout histogram
system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 4285000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------

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tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
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tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
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@@ -1,152 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1276946 # Simulator instruction rate (inst/s)
host_op_rate 1276946 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 638473293 # Simulator tick rate (ticks/s)
host_mem_usage 226984 # Number of bytes of host memory used
host_seconds 312.20 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory
system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory
system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory
system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory
system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520764 # DTB write accesses
system.cpu.dtb.data_hits 168275218 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664595 # Number of instructions committed
system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365907 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275274 # number of memory refs
system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_store_insts 73520764 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 398664824 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 44587532 # Number of branches fetched
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction
system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664651 # Class of executed instruction
system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 566939869 # Request fanout histogram
---------- End Simulation Statistics ----------

2892
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
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tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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@@ -1,991 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1039500 # Simulator instruction rate (inst/s)
host_op_rate 1039462 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 134594380 # Simulator tick rate (ticks/s)
host_mem_usage 262812 # Number of bytes of host memory used
host_seconds 0.65 # Real time elapsed on the host
sim_insts 677333 # Number of instructions simulated
sim_ops 677333 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 175326 # Number of instructions committed
system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
system.cpu0.num_int_insts 120376 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 82397 # number of memory refs
system.cpu0.num_load_insts 54591 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles
system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu0.Branches 29689 # Number of branches fetched
system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction
system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction
system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction
system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 175388 # Class of executed instruction
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
system.cpu0.dcache.overall_misses::total 328 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.icache.tags.replacements 215 # number of replacements
system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
system.cpu0.icache.overall_hits::total 174921 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
system.cpu0.icache.writebacks::total 215 # number of writebacks
system.cpu1.numCycles 173297 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 167400 # Number of instructions committed
system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls
system.cpu1.num_int_insts 107326 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read
system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 49494 # number of memory refs
system.cpu1.num_load_insts 39345 # Number of load instructions
system.cpu1.num_store_insts 10149 # Number of store instructions
system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles
system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles
system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles
system.cpu1.Branches 35694 # Number of branches fetched
system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction
system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction
system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction
system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 167432 # Class of executed instruction
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits
system.cpu1.dcache.overall_hits::total 49120 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses
system.cpu1.dcache.overall_misses::total 287 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.tags.replacements 278 # number of replacements
system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits
system.cpu1.icache.overall_hits::total 167074 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
system.cpu1.icache.overall_misses::total 358 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 278 # number of writebacks
system.cpu1.icache.writebacks::total 278 # number of writebacks
system.cpu2.numCycles 173296 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 167335 # Number of instructions committed
system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 633 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls
system.cpu2.num_int_insts 114196 # number of integer instructions
system.cpu2.num_fp_insts 0 # number of float instructions
system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read
system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu2.num_mem_refs 59830 # number of memory refs
system.cpu2.num_load_insts 42793 # Number of load instructions
system.cpu2.num_store_insts 17037 # Number of store instructions
system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles
system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles
system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
system.cpu2.Branches 32221 # Number of branches fetched
system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction
system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction
system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction
system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction
system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 167367 # Class of executed instruction
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits
system.cpu2.dcache.overall_hits::total 59499 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses
system.cpu2.dcache.overall_misses::total 255 # number of overall misses
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.tags.replacements 278 # number of replacements
system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits
system.cpu2.icache.overall_hits::total 167009 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
system.cpu2.icache.overall_misses::total 358 # number of overall misses
system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks 278 # number of writebacks
system.cpu2.icache.writebacks::total 278 # number of writebacks
system.cpu3.numCycles 173297 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 167272 # Number of instructions committed
system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 633 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls
system.cpu3.num_int_insts 113295 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read
system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu3.num_mem_refs 58510 # number of memory refs
system.cpu3.num_load_insts 42344 # Number of load instructions
system.cpu3.num_store_insts 16166 # Number of store instructions
system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles
system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles
system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles
system.cpu3.Branches 32639 # Number of branches fetched
system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction
system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction
system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction
system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction
system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 167304 # Class of executed instruction
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits
system.cpu3.dcache.overall_hits::total 58176 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses
system.cpu3.dcache.overall_misses::total 260 # number of overall misses
system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.tags.replacements 279 # number of replacements
system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits
system.cpu3.icache.overall_hits::total 166945 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
system.cpu3.icache.overall_misses::total 359 # number of overall misses
system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks 279 # number of writebacks
system.cpu3.icache.writebacks::total 279 # number of writebacks
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use
system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 19424 # Number of tag accesses
system.l2c.tags.data_accesses 19424 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 1220 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 3 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 1 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 559 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.membus.trans_dist::ReadResp 423 # Transaction distribution
system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
system.membus.trans_dist::ReadExReq 183 # Transaction distribution
system.membus.trans_dist::ReadExResp 136 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 879 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 879 # Request fanout histogram
system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 0 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram
---------- End Simulation Statistics ----------

1638
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
View File

File diff suppressed because it is too large Load Diff

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu
sim_ticks 10021833 # Number of ticks simulated
final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 141404 # Simulator tick rate (ticks/s)
host_mem_usage 425972 # Number of bytes of host memory used
host_seconds 70.87 # Real time elapsed on the host
host_tick_rate 162199 # Simulator tick rate (ticks/s)
host_mem_usage 417868 # Number of bytes of host memory used
host_seconds 61.79 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.007437 # Nu
sim_ticks 7436579 # Number of ticks simulated
final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 32317 # Simulator tick rate (ticks/s)
host_mem_usage 403848 # Number of bytes of host memory used
host_seconds 230.12 # Real time elapsed on the host
host_tick_rate 74529 # Simulator tick rate (ticks/s)
host_mem_usage 420508 # Number of bytes of host memory used
host_seconds 99.78 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.006099 # Nu
sim_ticks 6099346 # Number of ticks simulated
final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 34740 # Simulator tick rate (ticks/s)
host_mem_usage 404344 # Number of bytes of host memory used
host_seconds 175.57 # Real time elapsed on the host
host_tick_rate 81040 # Simulator tick rate (ticks/s)
host_mem_usage 421980 # Number of bytes of host memory used
host_seconds 75.26 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu
sim_ticks 4722948 # Number of ticks simulated
final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 43612 # Simulator tick rate (ticks/s)
host_mem_usage 429416 # Number of bytes of host memory used
host_seconds 108.30 # Real time elapsed on the host
host_tick_rate 53510 # Simulator tick rate (ticks/s)
host_mem_usage 421672 # Number of bytes of host memory used
host_seconds 88.26 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu
sim_ticks 7678882 # Number of ticks simulated
final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 131227 # Simulator tick rate (ticks/s)
host_mem_usage 425824 # Number of bytes of host memory used
host_seconds 58.52 # Real time elapsed on the host
host_tick_rate 120821 # Simulator tick rate (ticks/s)
host_mem_usage 418672 # Number of bytes of host memory used
host_seconds 63.56 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory

6
tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000502 # Nu
sim_ticks 501584000 # Number of ticks simulated
final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 112049096 # Simulator tick rate (ticks/s)
host_mem_usage 235328 # Number of bytes of host memory used
host_seconds 4.48 # Real time elapsed on the host
host_tick_rate 82658959 # Simulator tick rate (ticks/s)
host_mem_usage 231728 # Number of bytes of host memory used
host_seconds 6.07 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory

6
tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000500 # Nu
sim_ticks 500337000 # Number of ticks simulated
final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 94931123 # Simulator tick rate (ticks/s)
host_mem_usage 234040 # Number of bytes of host memory used
host_seconds 5.27 # Real time elapsed on the host
host_tick_rate 90464630 # Simulator tick rate (ticks/s)
host_mem_usage 231728 # Number of bytes of host memory used
host_seconds 5.53 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory

152
tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
View File

@@ -1,152 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1271644 # Simulator instruction rate (inst/s)
host_op_rate 1271643 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 636550745 # Simulator tick rate (ticks/s)
host_mem_usage 229384 # Number of bytes of host memory used
host_seconds 69.47 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory
system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory
system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory
system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory
system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.itb.fetch_hits 88438073 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 88442007 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
system.cpu.num_int_insts 78039444 # number of integer instructions
system.cpu.num_fp_insts 267757 # number of float instructions
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
system.cpu.num_mem_refs 34987415 # number of memory refs
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 88442007 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 123328088 # Request fanout histogram
---------- End Simulation Statistics ----------

546
tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View File

@@ -1,546 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.134742 # Number of seconds simulated
sim_ticks 134741611500 # Number of ticks simulated
final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1303886 # Simulator instruction rate (inst/s)
host_op_rate 1303885 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1988750581 # Simulator tick rate (ticks/s)
host_mem_usage 260188 # Number of bytes of host memory used
host_seconds 67.75 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory
system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory
system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory
system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory
system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.itb.fetch_hits 88438074 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 269483223 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
system.cpu.num_int_insts 78039444 # number of integer instructions
system.cpu.num_fp_insts 267757 # number of float instructions
system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
system.cpu.num_mem_refs 34987415 # number of memory refs
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 269483223 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
system.cpu.dcache.tags.replacements 200248 # number of replacements
system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks
system.cpu.dcache.writebacks::total 168278 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
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system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 131998 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 33266 # Transaction distribution
system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution
system.membus.trans_dist::CleanEvict 13845 # Transaction distribution
system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 292375 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 292375 # Request fanout histogram
system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------

243
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -1,243 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.048960 # Number of seconds simulated
sim_ticks 48960022500 # Number of ticks simulated
final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 991674 # Simulator instruction rate (inst/s)
host_op_rate 1268214 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 684673258 # Simulator tick rate (ticks/s)
host_mem_usage 242788 # Number of bytes of host memory used
host_seconds 71.51 # Real time elapsed on the host
sim_insts 70913204 # Number of instructions simulated
sim_ops 90688159 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 97920046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70913204 # Number of instructions committed
system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528528 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741468 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
system.membus.trans_dist::ReadReq 100925158 # Transaction distribution
system.membus.trans_dist::ReadResp 100941077 # Transaction distribution
system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930641 # Request fanout histogram
system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram
system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 120930641 # Request fanout histogram
---------- End Simulation Statistics ----------

662
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
View File

@@ -1,662 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.128077 # Number of seconds simulated
sim_ticks 128076834500 # Number of ticks simulated
final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 775777 # Simulator instruction rate (inst/s)
host_op_rate 990450 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1411878896 # Simulator tick rate (ticks/s)
host_mem_usage 277764 # Number of bytes of host memory used
host_seconds 90.71 # Real time elapsed on the host
sim_insts 70373651 # Number of instructions simulated
sim_ops 89847385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory
system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory
system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory
system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory
system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 256153669 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373651 # Number of instructions committed
system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528528 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741468 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
system.cpu.dcache.tags.replacements 155902 # number of replacements
system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits
system.cpu.dcache.overall_hits::total 42569839 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses
system.cpu.dcache.overall_misses::total 183873 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles
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system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses
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system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
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system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses
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system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles
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system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency
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system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use
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system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
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system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
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system.cpu.icache.overall_hits::total 78126184 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
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system.cpu.icache.overall_misses::total 18908 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses
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system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 95333 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id
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system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits
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system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits
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system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits
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system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits
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system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses
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system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses
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system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses
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system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles
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system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses)
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks
system.cpu.l2cache.writebacks::total 86150 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 95333 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 25194 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution
system.membus.trans_dist::CleanEvict 6168 # Transaction distribution
system.membus.trans_dist::ReadExReq 102281 # Transaction distribution
system.membus.trans_dist::ReadExResp 102281 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 219817 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 219817 # Request fanout histogram
system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

124
tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View File

@@ -1,124 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148677000 # Number of ticks simulated
final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1843276 # Simulator instruction rate (inst/s)
host_op_rate 1867142 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 934655607 # Simulator tick rate (ticks/s)
host_mem_usage 225200 # Number of bytes of host memory used
host_seconds 72.91 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297355 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398959 # Number of instructions committed
system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187757 # number of integer instructions
system.cpu.num_fp_insts 2326976 # number of float instructions
system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160261 # number of memory refs
system.cpu.num_load_insts 37275864 # Number of load instructions
system.cpu.num_store_insts 20884397 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719094 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293808 # Class of executed instruction
system.membus.trans_dist::ReadReq 171784880 # Transaction distribution
system.membus.trans_dist::ReadResp 171784880 # Transaction distribution
system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
system.membus.trans_dist::SwapReq 15916 # Transaction distribution
system.membus.trans_dist::SwapResp 15916 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 192665100 # Request fanout histogram
system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 192665100 # Request fanout histogram
---------- End Simulation Statistics ----------

535
tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View File

@@ -1,535 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.203116 # Number of seconds simulated
sim_ticks 203115946500 # Number of ticks simulated
final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1277402 # Simulator instruction rate (inst/s)
host_op_rate 1293942 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1930526358 # Simulator tick rate (ticks/s)
host_mem_usage 259920 # Number of bytes of host memory used
host_seconds 105.21 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory
system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory
system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory
system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 406231893 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398959 # Number of instructions committed
system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187757 # number of integer instructions
system.cpu.num_fp_insts 2326976 # number of float instructions
system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160261 # number of memory refs
system.cpu.num_load_insts 37275864 # Number of load instructions
system.cpu.num_store_insts 20884397 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719094 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293808 # Class of executed instruction
system.cpu.dcache.tags.replacements 146583 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits
system.cpu.dcache.overall_hits::total 57944940 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses
system.cpu.dcache.overall_misses::total 150664 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks
system.cpu.dcache.writebacks::total 123865 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
system.cpu.icache.tags.replacements 184976 # number of replacements
system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses
system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits
system.cpu.icache.overall_hits::total 134366557 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
system.cpu.icache.overall_misses::total 187024 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 184976 # number of writebacks
system.cpu.icache.writebacks::total 184976 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 99022 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits
system.cpu.l2cache.overall_hits::total 207181 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses
system.cpu.l2cache.overall_misses::total 130522 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks
system.cpu.l2cache.writebacks::total 85270 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 99022 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 29258 # Transaction distribution
system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution
system.membus.trans_dist::CleanEvict 10301 # Transaction distribution
system.membus.trans_dist::ReadExReq 101264 # Transaction distribution
system.membus.trans_dist::ReadExResp 101264 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 226093 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 226093 # Request fanout histogram
system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

6
tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.010000 # Nu
sim_ticks 10000000000 # Number of ticks simulated
final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 995173175 # Simulator tick rate (ticks/s)
host_mem_usage 1449604 # Number of bytes of host memory used
host_seconds 10.05 # Real time elapsed on the host
host_tick_rate 621801419 # Simulator tick rate (ticks/s)
host_mem_usage 1442452 # Number of bytes of host memory used
host_seconds 16.08 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::l0subsys0.tester0 2151552 # Number of bytes read from this memory

6
tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000014 # Nu
sim_ticks 14181 # Number of ticks simulated
final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 116506 # Simulator tick rate (ticks/s)
host_mem_usage 464616 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_tick_rate 154609 # Simulator tick rate (ticks/s)
host_mem_usage 480252 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory

6
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000043 # Nu
sim_ticks 43191 # Number of ticks simulated
final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 428274 # Simulator tick rate (ticks/s)
host_mem_usage 410016 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 667875 # Simulator tick rate (ticks/s)
host_mem_usage 406088 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory

6
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu
sim_ticks 54211 # Number of ticks simulated
final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 316777 # Simulator tick rate (ticks/s)
host_mem_usage 410608 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_tick_rate 538772 # Simulator tick rate (ticks/s)
host_mem_usage 406688 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory

6
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000050 # Nu
sim_ticks 50141 # Number of ticks simulated
final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 395128 # Simulator tick rate (ticks/s)
host_mem_usage 389312 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 969830 # Simulator tick rate (ticks/s)
host_mem_usage 406616 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory

6
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000030 # Nu
sim_ticks 29561 # Number of ticks simulated
final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 334780 # Simulator tick rate (ticks/s)
host_mem_usage 410240 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 593739 # Simulator tick rate (ticks/s)
host_mem_usage 406316 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory

6
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.000038 # Nu
sim_ticks 37741 # Number of ticks simulated
final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 544029 # Simulator tick rate (ticks/s)
host_mem_usage 408776 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 877206 # Simulator tick rate (ticks/s)
host_mem_usage 404076 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory

6
tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 4618007467 # Simulator tick rate (ticks/s)
host_mem_usage 202228 # Number of bytes of host memory used
host_seconds 21.65 # Real time elapsed on the host
host_tick_rate 9064709748 # Simulator tick rate (ticks/s)
host_mem_usage 219696 # Number of bytes of host memory used
host_seconds 11.03 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory

6
tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
View File

@@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 15880275218 # Simulator tick rate (ticks/s)
host_mem_usage 204660 # Number of bytes of host memory used
host_seconds 6.30 # Real time elapsed on the host
host_tick_rate 16220790107 # Simulator tick rate (ticks/s)
host_mem_usage 221740 # Number of bytes of host memory used
host_seconds 6.17 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory

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