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fixes for newmem

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ALPHA_FS finally compiles again

SConscript:
    Use a couple more FS sources, still don't compile that much
arch/alpha/faults.hh:
    the unimp fault should probably exist in nonfs too.
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/simconsole.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
sim/process.cc:
sim/system.cc:
    fixes for newmem
dev/io_device.hh:
    a system pointer is probably useful for every device to have
mem/bus.hh:
mem/physical.cc:
    new address ranges function
python/m5/objects/SimpleDisk.py:
    simple disk now has a system pointer rather than physmem directly

--HG--
extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
This commit is contained in:
Ali Saidi
2006-04-06 14:57:51 -04:00
parent bb80f71f21
commit 6240f8c4bc
17 changed files with 131 additions and 141 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
dev/alpha_console.cc
View File

@@ -53,7 +53,7 @@ using namespace AlphaISA;
AlphaConsole::AlphaConsole(Params *p)
: BasicPioDevice(p), disk(p->disk),
console(params()->cons), system(params()->sys), cpu(params()->cpu)
console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
{
pioSize = sizeof(struct AlphaAccess);
@@ -99,7 +99,6 @@ AlphaConsole::addressRanges(AddrRangeList &range_list)
Tick
AlphaConsole::read(Packet &pkt)
{
pkt.time = curTick + pioDelay;
/** XXX Do we want to push the addr munging to a bus brige or something? So
* the device has it's physical address and then the bridge adds on whatever
@@ -108,6 +107,8 @@ AlphaConsole::read(Packet &pkt)
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
Addr daddr = pkt.addr - pioAddr;
uint32_t *data32;
@@ -355,7 +356,8 @@ CREATE_SIM_OBJECT(AlphaConsole)
p->pio_delay = pio_latency;
p->cons = sim_console;
p->disk = disk;
p->sys = system;
p->alpha_sys = system;
p->system = system;
p->cpu = cpu;
return new AlphaConsole(p);
}

2
dev/alpha_console.hh
View File

@@ -100,7 +100,7 @@ class AlphaConsole : public BasicPioDevice
{
SimConsole *cons;
SimpleDisk *disk;
AlphaSystem *sys;
AlphaSystem *alpha_sys;
BaseCPU *cpu;
};
protected:

2
dev/io_device.hh
View File

@@ -37,6 +37,7 @@
class Platform;
class PioDevice;
class DmaDevice;
class System;
/**
* The PioPort class is a programmed i/o port that all devices that are
@@ -207,6 +208,7 @@ class PioDevice : public SimObject
{
std::string name;
Platform *platform;
System *system;
};
protected:

1
dev/simconsole.cc
View File

@@ -49,7 +49,6 @@
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;

22
dev/simple_disk.cc
View File

@@ -42,14 +42,14 @@
#include "base/trace.hh"
#include "dev/disk_image.hh"
#include "dev/simple_disk.hh"
#include "mem/functional/physical.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
SimpleDisk::SimpleDisk(const string &name, PhysicalMemory *pmem,
DiskImage *img)
: SimObject(name), physmem(pmem), image(img)
SimpleDisk::SimpleDisk(const string &name, System *sys, DiskImage *img)
: SimObject(name), system(sys), image(img)
{}
SimpleDisk::~SimpleDisk()
@@ -59,9 +59,7 @@ SimpleDisk::~SimpleDisk()
void
SimpleDisk::read(Addr addr, baddr_t block, int count) const
{
uint8_t *data = physmem->dma_addr(addr, count);
if (!data)
panic("dma out of range! read addr=%#x count=%d\n", addr, count);
uint8_t *data = new uint8_t[SectorSize * count];
if (count & (SectorSize - 1))
panic("Not reading a multiple of a sector (count = %d)", count);
@@ -69,8 +67,12 @@ SimpleDisk::read(Addr addr, baddr_t block, int count) const
for (int i = 0, j = 0; i < count; i += SectorSize, j++)
image->read(data + i, block + j);
system->functionalPort.writeBlob(addr, data, count);
DPRINTF(SimpleDisk, "read block=%#x len=%d\n", (uint64_t)block, count);
DDUMP(SimpleDiskData, data, count);
delete data;
}
void
@@ -89,21 +91,21 @@ SimpleDisk::write(Addr addr, baddr_t block, int count)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
SimObjectParam<PhysicalMemory *> physmem;
SimObjectParam<System *> system;
SimObjectParam<DiskImage *> disk;
END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
INIT_PARAM(physmem, "Physical Memory"),
INIT_PARAM(system, "System pointer"),
INIT_PARAM(disk, "Disk Image")
END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
CREATE_SIM_OBJECT(SimpleDisk)
{
return new SimpleDisk(getInstanceName(), physmem, disk);
return new SimpleDisk(getInstanceName(), system, disk);
}
REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)

6
dev/simple_disk.hh
View File

@@ -37,7 +37,7 @@
#include "arch/isa_traits.hh"
class DiskImage;
class PhysicalMemory;
class System;
/*
* Trivial interface to a disk image used by the System Console
@@ -48,11 +48,11 @@ class SimpleDisk : public SimObject
typedef uint64_t baddr_t;
protected:
PhysicalMemory *physmem;
System *system;
DiskImage *image;
public:
SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
SimpleDisk(const std::string &name, System *sys, DiskImage *img);
~SimpleDisk();
void read(Addr addr, baddr_t block, int count) const;

32
dev/uart.cc
View File

@@ -27,39 +27,19 @@
*/
/** @file
* Implements a 8250 UART
* Implements a base class for UARTs
*/
#include <string>
#include <vector>
#include "base/inifile.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "dev/platform.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
: PioDevice(name, p), addr(a), size(s), cons(c)
Uart::Uart(Params *p)
: BasicPioDevice(p), platform(p->platform), cons(p->cons)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&Uart::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
}
status = 0;
@@ -68,11 +48,5 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
platform->uart = this;
}
Tick
Uart::cacheAccess(MemReqPtr &req)
{
return curTick + pioLatency;
}
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)

26
dev/uart.hh
View File

@@ -37,30 +37,27 @@
#include "dev/io_device.hh"
class SimConsole;
class MemoryController;
class Platform;
const int RX_INT = 0x1;
const int TX_INT = 0x2;
class Uart : public PioDevice
class Uart : public BasicPioDevice
{
protected:
int status;
Addr addr;
Addr size;
Platform *platform;
SimConsole *cons;
public:
Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
struct Params : public BasicPioDevice::Params
{
SimConsole *cons;
};
Uart(Params *p);
/**
* Inform the uart that there is data available.
@@ -74,12 +71,9 @@ class Uart : public PioDevice
*/
bool intStatus() { return status ? true : false; }
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
protected:
const Params *params() const {return (const Params *)_params; }
};
#endif // __UART_HH__

120
dev/uart8250.cc
View File

@@ -40,10 +40,6 @@
#include "dev/simconsole.hh"
#include "dev/uart8250.hh"
#include "dev/platform.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
@@ -100,26 +96,35 @@ Uart8250::IntrEvent::scheduleIntr()
}
Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *pio_bus,
Tick pio_latency, Platform *p)
: Uart(name, c, mmu, a, s, hier, pio_bus, pio_latency, p),
txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
Uart8250::Uart8250(Params *p)
: Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
{
pioSize = 8;
IER = 0;
DLAB = 0;
LCR = 0;
MCR = 0;
}
Fault
Uart8250::read(MemReqPtr &req, uint8_t *data)
Tick
Uart8250::read(Packet &pkt)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
assert(pkt.result == Unknown);
assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
assert(pkt.size == 1);
pkt.time = curTick + pioDelay;
Addr daddr = pkt.addr - pioAddr;
uint8_t *data;
DPRINTF(Uart, " read register %#x\n", daddr);
assert(req->size == 1);
if (!pkt.data) {
data = new uint8_t;
pkt.data = data;
} else
data = pkt.data;
switch (daddr) {
case 0x0:
@@ -127,7 +132,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
if (cons->dataAvailable())
cons->in(*data);
else {
*(uint8_t*)data = 0;
*data = 0;
// A limited amount of these are ok.
DPRINTF(Uart, "empty read of RX register\n");
}
@@ -142,7 +147,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
break;
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
*(uint8_t*)data = IER;
*data = IER;
} else { // DLM divisor latch MSB
;
}
@@ -151,17 +156,17 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
if (status & RX_INT) /* Rx data interrupt has a higher priority */
*(uint8_t*)data = IIR_RXID;
*data = IIR_RXID;
else if (status & TX_INT)
*(uint8_t*)data = IIR_TXID;
*data = IIR_TXID;
else
*(uint8_t*)data = IIR_NOPEND;
*data = IIR_NOPEND;
//Tx interrupts are cleared on IIR reads
status &= ~TX_INT;
break;
case 0x3: // Line Control Register (LCR)
*(uint8_t*)data = LCR;
*data = LCR;
break;
case 0x4: // Modem Control Register (MCR)
break;
@@ -172,34 +177,41 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
if (cons->dataAvailable())
lsr = UART_LSR_DR;
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
*(uint8_t*)data = lsr;
*data = lsr;
break;
case 0x6: // Modem Status Register (MSR)
*(uint8_t*)data = 0;
*data = 0;
break;
case 0x7: // Scratch Register (SCR)
*(uint8_t*)data = 0; // doesn't exist with at 8250.
*data = 0; // doesn't exist with at 8250.
break;
default:
panic("Tried to access a UART port that doesn't exist\n");
break;
}
return NoFault;
return pioDelay;
}
Fault
Uart8250::write(MemReqPtr &req, const uint8_t *data)
Tick
Uart8250::write(Packet &pkt)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
assert(pkt.size == 1);
pkt.time = curTick + pioDelay;
Addr daddr = pkt.addr - pioAddr;
uint8_t *data = pkt.data;
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *data);
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
cons->out(*(uint8_t *)data);
cons->out(*data);
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
@@ -210,7 +222,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
break;
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
IER = *(uint8_t*)data;
IER = *data;
if (UART_IER_THRI & IER)
{
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
@@ -244,10 +256,10 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
case 0x2: // FIFO Control Register (FCR)
break;
case 0x3: // Line Control Register (LCR)
LCR = *(uint8_t*)data;
LCR = *data;
break;
case 0x4: // Modem Control Register (MCR)
if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
if (*data == (UART_MCR_LOOP | 0x0A))
MCR = 0x9A;
break;
case 0x7: // Scratch Register (SCR)
@@ -257,7 +269,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
return NoFault;
return pioDelay;
}
void
@@ -272,6 +284,14 @@ Uart8250::dataAvailable()
}
void
Uart8250::addressRanges(AddrRangeList &range_list)
{
assert(pioSize != 0);
range_list.clear();
range_list.push_back(RangeSize(pioAddr, pioSize));
}
void
@@ -316,35 +336,35 @@ Uart8250::unserialize(Checkpoint *cp, const std::string &section)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
SimObjectParam<SimConsole *> console;
SimObjectParam<MemoryController *> mmu;
SimObjectParam<Platform *> platform;
Param<Addr> addr;
Param<Addr> size;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
SimObjectParam<Platform *> platform;
SimObjectParam<SimConsole *> sim_console;
SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
INIT_PARAM(console, "The console"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(platform, "Pointer to platfrom"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(size, "Device size", 0x8),
INIT_PARAM(pio_bus, ""),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
INIT_PARAM(platform, "platform"),
INIT_PARAM(sim_console, "The Simulator Console"),
INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(Uart8250)
CREATE_SIM_OBJECT(Uart8250)
{
return new Uart8250(getInstanceName(), console, mmu, addr, size, hier,
pio_bus, pio_latency, platform);
Uart8250::Params *p = new Uart8250::Params;
p->name = getInstanceName();
p->pio_addr = addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->cons = sim_console;
p->system = system;
return new Uart8250(p);
}
REGISTER_SIM_OBJECT("Uart8250", Uart8250)

14
dev/uart8250.hh
View File

@@ -30,8 +30,8 @@
* Defines a 8250 UART
*/
#ifndef __TSUNAMI_UART_HH__
#define __TSUNAMI_UART_HH__
#ifndef __DEV_UART8250_HH__
#define __DEV_UART8250_HH__
#include "dev/tsunamireg.h"
#include "base/range.hh"
@@ -53,7 +53,6 @@
#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
class SimConsole;
class MemoryController;
class Platform;
class Uart8250 : public Uart
@@ -79,12 +78,11 @@ class Uart8250 : public Uart
IntrEvent rxIntrEvent;
public:
Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
Platform *p);
Uart8250(Params *p);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Tick read(Packet &pkt);
virtual Tick write(Packet &pkt);
virtual void addressRanges(AddrRangeList &range_list);
/**