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mem: Add an HBM memory controller

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This change adds an hbm memory controller in gem5,
which is capable of controlling two hbm memory interfaces
(two pseudo channels). HBMCtrl inherits from MemCtrl
and tries to reuse most of the MemCtrl functions for two
different dram interfaces. Morever, a notion of pseudo
channel is added in the memory interface itself, to make
sure that the scheduling decisions in any interface are
based on the pkts for that pseudo channel only. Also, the
command bandwidth checks are divided into row and column
commands, which are shared by both pseudo channels.

Change-Id: Ie2ee8183d0f7f744aff2ed05cabc75fec3ea2171
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59732
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
2022-05-13 23:20:14 -07:00
committed by Bobby Bruce
parent b0fd05dd3d
commit 60317f99fe
14 changed files with 920 additions and 62 deletions
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2
src/mem/SConscript
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@@ -51,6 +51,7 @@ DebugFlag('SysBridge')
SimObject('MemCtrl.py', sim_objects=['MemCtrl'],
enums=['MemSched'])
SimObject('HeteroMemCtrl.py', sim_objects=['HeteroMemCtrl'])
SimObject('HBMCtrl.py', sim_objects=['HBMCtrl'])
SimObject('MemInterface.py', sim_objects=['MemInterface'], enums=['AddrMap'])
SimObject('DRAMInterface.py', sim_objects=['DRAMInterface'],
enums=['PageManage'])
@@ -77,6 +78,7 @@ Source('external_master.cc')
Source('external_slave.cc')
Source('mem_ctrl.cc')
Source('hetero_mem_ctrl.cc')
Source('hbm_ctrl.cc')
Source('mem_interface.cc')
Source('dram_interface.cc')
Source('nvm_interface.cc')