derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface

Browse Source 
--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
This commit is contained in:
Ron Dreslinski
2005-04-29 21:01:43 -04:00
parent e07fee31cb
commit 602a489573
6 changed files with 25 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
python/m5/objects/Ethernet.mpy
View File

@@ -41,6 +41,7 @@ simobj EtherDev(DmaDevice):
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Latency('1us', "Receive Delay")
@@ -64,6 +65,8 @@ simobj NSGigE(PciDevice):
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Latency('1us', "Receive Delay")