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Fix bugs due to interaction between SEV instructions and O3 pipeline

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SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
This commit is contained in:
Geoffrey Blake
2011-08-19 15:08:07 -05:00
parent f125ef22b9
commit 5f425b8bd1
9 changed files with 92 additions and 12 deletions
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1
src/cpu/o3/commit_impl.hh
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@@ -505,6 +505,7 @@ DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
cpu->schedule(trap, curTick() + trapLatency);
trapInFlight[tid] = true;
thread[tid]->trapPending = true;
}
template <class Impl>

16
src/cpu/o3/cpu.hh
View File

@@ -184,9 +184,19 @@ class FullO3CPU : public BaseO3CPU
if (activateThreadEvent[tid].squashed())
reschedule(activateThreadEvent[tid],
nextCycle(curTick() + ticks(delay)));
else if (!activateThreadEvent[tid].scheduled())
schedule(activateThreadEvent[tid],
nextCycle(curTick() + ticks(delay)));
else if (!activateThreadEvent[tid].scheduled()) {
Tick when = nextCycle(curTick() + ticks(delay));
// Check if the deallocateEvent is also scheduled, and make
// sure they do not happen at same time causing a sleep that
// is never woken from.
if (deallocateContextEvent[tid].scheduled() &&
deallocateContextEvent[tid].when() == when) {
when++;
}
schedule(activateThreadEvent[tid], when);
}
}
/** Unschedule actiavte thread event, regardless of its current state. */

3
src/cpu/o3/thread_context_impl.hh
View File

@@ -351,8 +351,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg,
const MiscReg &val)
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());