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arch: cpu: Rename *FloatRegBits* to *FloatReg*.

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Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-19 18:14:16 -08:00
parent 25474167e5
commit 5edfb67041
42 changed files with 143 additions and 145 deletions
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8
src/cpu/thread_context.cc
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@@ -71,8 +71,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
RegVal t1 = one->readFloatRegBits(i);
RegVal t2 = two->readFloatRegBits(i);
RegVal t1 = one->readFloatReg(i);
RegVal t2 = two->readFloatReg(i);
if (t1 != t2)
panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -169,7 +169,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp)
RegVal floatRegs[NumFloatRegs];
for (int i = 0; i < NumFloatRegs; ++i)
floatRegs[i] = tc.readFloatRegBitsFlat(i);
floatRegs[i] = tc.readFloatRegFlat(i);
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
@@ -213,7 +213,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
// compatibility.
arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
for (int i = 0; i < NumFloatRegs; ++i)
tc.setFloatRegBitsFlat(i, floatRegs[i]);
tc.setFloatRegFlat(i, floatRegs[i]);
std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
UNSERIALIZE_CONTAINER(vecRegs);