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arch: cpu: Rename *FloatRegBits* to *FloatReg*.

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Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-19 18:14:16 -08:00
parent 25474167e5
commit 5edfb67041
42 changed files with 143 additions and 145 deletions
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12
src/cpu/simple_thread.hh
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@@ -255,11 +255,11 @@ class SimpleThread : public ThreadState
}
RegVal
readFloatRegBits(int reg_idx)
readFloatReg(int reg_idx)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
RegVal regVal(readFloatRegBitsFlat(flatIndex));
RegVal regVal(readFloatRegFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
@@ -406,14 +406,14 @@ class SimpleThread : public ThreadState
}
void
setFloatRegBits(int reg_idx, RegVal val)
setFloatReg(int reg_idx, RegVal val)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
// XXX: Fix array out of bounds compiler error for gem5.fast
// when checkercpu enabled
if (flatIndex < TheISA::NumFloatRegs)
setFloatRegBitsFlat(flatIndex, val);
setFloatRegFlat(flatIndex, val);
DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
reg_idx, flatIndex, val);
}
@@ -558,8 +558,8 @@ class SimpleThread : public ThreadState
RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; }
RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; }
void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; }
const VecRegContainer &
readVecRegFlat(const RegIndex& reg) const