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arch: cpu: Rename *FloatRegBits* to *FloatReg*.

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Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-19 18:14:16 -08:00
parent 25474167e5
commit 5edfb67041
42 changed files with 143 additions and 145 deletions
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8
src/cpu/o3/thread_context_impl.hh
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@@ -205,9 +205,9 @@ O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
template <class Impl>
RegVal
O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
{
return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
return cpu->readArchFloatReg(reg_idx, thread->threadId());
}
template <class Impl>
@@ -264,9 +264,9 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
template <class Impl>
void
O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val)
O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val)
{
cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
cpu->setArchFloatReg(reg_idx, val, thread->threadId());
conditionalSquash();
}