From 5eb73551bda1ecdc632cf50f27eb45ff2dbf1bfa Mon Sep 17 00:00:00 2001 From: Yu-hsin Wang Date: Mon, 14 Nov 2022 16:11:57 +0800 Subject: [PATCH] fastmodel: CortexR52 export standbywfi signal Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65534 Reviewed-by: Gabe Black Tested-by: kokoro Maintainer: Gabe Black --- .../fastmodel/CortexR52/FastModelCortexR52.py | 5 ++- .../arm/fastmodel/CortexR52/cortex_r52.cc | 4 ++ src/arch/arm/fastmodel/CortexR52/evs.cc | 10 +++++ src/arch/arm/fastmodel/CortexR52/evs.hh | 1 + src/arch/arm/fastmodel/CortexR52/x1/x1.lisa | 4 ++ src/arch/arm/fastmodel/CortexR52/x2/x2.lisa | 4 ++ src/arch/arm/fastmodel/CortexR52/x3/x3.lisa | 4 ++ src/arch/arm/fastmodel/CortexR52/x4/x4.lisa | 4 ++ .../arm/fastmodel/common/signal_receiver.hh | 37 +++++++++++++++++++ 9 files changed, 72 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py index 4970ae2ed4..1e267f028f 100644 --- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py +++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py @@ -31,7 +31,7 @@ from m5.objects.ArmInterrupts import ArmInterrupts from m5.objects.ArmISA import ArmISA from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket from m5.objects.ResetPort import ResetResponsePort -from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin +from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin from m5.objects.Iris import IrisBaseCPU from m5.objects.SystemC import SystemC_ScModule @@ -56,6 +56,9 @@ class FastModelCortexR52(IrisBaseCPU): "processor logic, including debug logic." ) halt = IntSinkPin("Raising this signal will put the core into halt mode.") + standbywfi = IntSourcePin( + "This signal indicates if a core is in WFI state." + ) CFGEND = Param.Bool( False, diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc index be83082d16..9dfe7a5158 100644 --- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc +++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc @@ -92,6 +92,10 @@ CortexR52::getPort(const std::string &if_name, PortID idx) // Since PPIs are indexed both by core and by number, modify the name // to hold the core number. return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx); + } else if (if_name == "standbywfi") { + // Since standbywfi is indexed by fanout, modify the name to hold the + // core number. + return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx); } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash" || if_name == "core_reset" || if_name == "poweron_reset" || if_name == "halt") { diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc index 6887c6ced9..734323e026 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.cc +++ b/src/arch/arm/fastmodel/CortexR52/evs.cc @@ -79,6 +79,7 @@ ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) : core_reset(name + ".core_reset", 0), poweron_reset(name + ".poweron_reset", 0), halt(name + ".halt", 0), + standbywfi(name + ".standbywfi"), cfgvectable((name + "cfgvectable").c_str()) { for (int i = 0; i < Evs::PpiCount; i++) { @@ -88,6 +89,7 @@ ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) : core_reset.signal_out.bind(evs->core_reset[cpu]); poweron_reset.signal_out.bind(evs->poweron_reset[cpu]); halt.signal_out.bind(evs->halt[cpu]); + evs->standbywfi[cpu].bind(standbywfi.signal_in); cfgvectable.bind(evs->cfgvectable[cpu]); } @@ -161,6 +163,14 @@ ScxEvsCortexR52::gem5_getPort(const std::string &if_name, int idx) panic("Couldn't find CPU number in %s.", if_name); } return *this->corePins.at(cpu)->ppis.at(idx); + } else if (if_name.substr(0, 10) == "standbywfi") { + int cpu; + try { + cpu = std::stoi(if_name.substr(11)); + } catch (const std::invalid_argument &a) { + panic("Couldn't find CPU number in %s.", if_name); + } + return this->corePins.at(cpu)->standbywfi.getSignalOut(idx); } else { return Base::gem5_getPort(if_name, idx); } diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh index 535d678c34..02ef1ae257 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.hh +++ b/src/arch/arm/fastmodel/CortexR52/evs.hh @@ -110,6 +110,7 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs SignalSender core_reset; SignalSender poweron_reset; SignalSender halt; + SignalReceiverInt standbywfi; SignalInitiator cfgvectable; }; diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa index 2a7299d77e..2738ba23f9 100644 --- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa @@ -53,6 +53,9 @@ component CortexR52x1 self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -79,6 +82,7 @@ component CortexR52x1 slave port core_reset[1]; slave port poweron_reset[1]; slave port halt[1]; + master port standbywfi[1]; slave port top_reset; slave port dbg_reset; slave port cfgvectable[1]; diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa index 9100a5bcc2..485ffee983 100644 --- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa @@ -53,6 +53,9 @@ component CortexR52x2 self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -80,6 +83,7 @@ component CortexR52x2 slave port core_reset[2]; slave port poweron_reset[2]; slave port halt[2]; + master port standbywfi[2]; slave port top_reset; slave port dbg_reset; slave port cfgvectable[2]; diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa index bb8d153f44..1e526d9958 100644 --- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa @@ -53,6 +53,9 @@ component CortexR52x3 self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -81,6 +84,7 @@ component CortexR52x3 slave port core_reset[3]; slave port poweron_reset[3]; slave port halt[3]; + master port standbywfi[3]; slave port top_reset; slave port dbg_reset; slave port cfgvectable[3]; diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa index 5b278ddb41..df23bf17b4 100644 --- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa @@ -53,6 +53,9 @@ component CortexR52x4 self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -82,6 +85,7 @@ component CortexR52x4 slave port core_reset[4]; slave port poweron_reset[4]; slave port halt[4]; + master port standbywfi[4]; slave port top_reset; slave port dbg_reset; slave port cfgvectable[4]; diff --git a/src/arch/arm/fastmodel/common/signal_receiver.hh b/src/arch/arm/fastmodel/common/signal_receiver.hh index 0025e39173..990787743b 100644 --- a/src/arch/arm/fastmodel/common/signal_receiver.hh +++ b/src/arch/arm/fastmodel/common/signal_receiver.hh @@ -34,8 +34,12 @@ #pragma GCC diagnostic pop #include +#include #include "base/compiler.hh" +#include "base/cprintf.hh" +#include "base/types.hh" +#include "dev/intpin.hh" namespace gem5 { @@ -80,6 +84,39 @@ class SignalReceiver : public amba_pv::signal_slave_base } }; +class SignalReceiverInt : public SignalReceiver +{ + public: + using IntPin = IntSourcePin; + + explicit SignalReceiverInt(const std::string &name) + : SignalReceiver(name) + { + onChange([this](bool status) { + for (auto &signal : signalOut) { + if (signal && signal->isConnected()) + status ? signal->raise() : signal->lower(); + } + }); + } + + IntPin & + getSignalOut(int idx) + { + if (signalOut.size() <= idx) { + signalOut.resize(idx + 1); + } + if (!signalOut[idx]) { + signalOut[idx] = std::make_unique( + csprintf("%s.signalOut[%d]", get_name(), idx), idx, this); + } + return *signalOut[idx]; + } + + private: + std::vector> signalOut; +}; + } // namespace fastmodel } // namespace gem5