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Make the notion of a global event tick independent of the actual

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CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
This commit is contained in:
Nathan Binkert
2005-04-11 15:32:06 -04:00
parent 61a20bc32d
commit 5eab6c4b41
42 changed files with 301 additions and 164 deletions
Download Patch File Download Diff File Expand all files Collapse all files

102
python/m5/config.py
View File

@@ -265,7 +265,6 @@ def isParamContext(value):
except:
return False
class_decorator = 'M5M5_SIMOBJECT_'
expr_decorator = 'M5M5_EXPRESSION_'
dot_decorator = '_M5M5_DOT_'
@@ -652,6 +651,14 @@ class Node(object):
'parent.any matched more than one: %s %s' % \
(obj.path, child.path)
obj = child
for param in self.params:
if isConfigNode(param.ptype):
continue
if issubclass(param.ptype, realtype):
if obj is not None:
raise AttributeError, \
'parent.any matched more than one: %s' % obj.path
obj = param.value
return obj, obj is not None
try:
@@ -672,7 +679,7 @@ class Node(object):
return Proxy.getindex(value, index), True
elif obj.param_names.has_key(last):
value = obj.param_names[last]
realtype._convert(value.value)
#realtype._convert(value.value)
return Proxy.getindex(value.value, index), True
except KeyError:
pass
@@ -731,9 +738,18 @@ class Node(object):
raise AttributeError, 'Parameter with no value'
value = param.convert(param.value)
if hasattr(value, 'relative') and value.relative and value:
if param.name == 'cycle_time':
start = self.parent
else:
start = self
val = start.unproxy(parent.cycle_time,
(Frequency, Latency, ClockPeriod))
value.clock = Frequency._convert(val)
string = param.string(value)
except Exception, e:
msg = 'exception in %s:%s\n%s' % (self.path, param.name, e)
msg = 'exception in %s:%s=%s\n%s' % (self.path, param.name,
value, e)
e.args = (msg, )
raise
@@ -765,6 +781,9 @@ class Node(object):
raise AttributeError, 'Parameter with no value'
value = param.convert(param.value)
if param.ptype in (Frequency, Latency, ClockPeriod):
val = self.parent.unproxy(parent.frequency, Frequency)
param.clock = Frequency._convert(val)
string = param.string(value)
except Exception, e:
msg = 'exception in %s:%s\n%s' % (self.name, param.name, e)
@@ -1382,27 +1401,33 @@ class RootFrequency(float,ParamType):
_convert = classmethod(_convert)
def _string(cls, value):
return '%d' % int(value)
return '%d' % int(round(value))
_string = classmethod(_string)
class ClockPeriod(float,ParamType):
_cpp_param_decl = 'Tick'
def __new__(cls, value):
absolute = False
relative = False
try:
val = toClockPeriod(value)
except ValueError, e:
relative = True
if value.endswith('f'):
val = float(value[:-1])
if val:
val = 1 / val
relative = True
elif value.endswith('c'):
val = float(value[:-1])
relative = True
elif value.endswith('t'):
val = float(value[:-1])
absolute = True
else:
raise e
self = super(cls, ClockPeriod).__new__(cls, val)
self.absolute = absolute
self.relative = relative
return self
@@ -1411,10 +1436,14 @@ class ClockPeriod(float,ParamType):
_convert = classmethod(_convert)
def _string(cls, value):
if not value.relative:
value *= root_frequency
if value and not value.absolute:
if value.relative:
base = root_frequency / value.clock
else:
base = root_frequency
value *= base
return '%d' % int(value)
return '%d' % int(round(value))
_string = classmethod(_string)
class Frequency(float,ParamType):
@@ -1439,15 +1468,21 @@ class Frequency(float,ParamType):
_convert = classmethod(_convert)
def _string(cls, value):
if not value.relative:
value = root_frequency / value
if value:
if value.relative:
base = root_frequency / value.clock
else:
base = root_frequency
return '%d' % int(value)
value = base / value
return '%d' % int(round(value))
_string = classmethod(_string)
class Latency(float,ParamType):
_cpp_param_decl = 'Tick'
def __new__(cls, value):
absolute = False
relative = False
try:
val = toLatency(value)
@@ -1455,9 +1490,13 @@ class Latency(float,ParamType):
if value.endswith('c'):
val = float(value[:-1])
relative = True
elif value.endswith('t'):
val = float(value[:-1])
absolute = True
else:
raise e
self = super(cls, Latency).__new__(cls, val)
self.absolute = absolute
self.relative = relative
return self
@@ -1466,11 +1505,44 @@ class Latency(float,ParamType):
_convert = classmethod(_convert)
def _string(cls, value):
if not value.relative:
value *= root_frequency
return '%d' % value
if value and not value.absolute:
if value.relative:
base = root_frequency / value.clock
else:
base = root_frequency
value *= base
return '%d' % int(round(value))
_string = classmethod(_string)
class NetworkBandwidth(float,ParamType):
_cpp_param_decl = 'float'
def __new__(cls, value):
val = toNetworkBandwidth(value) / 8.0
return super(cls, NetworkBandwidth).__new__(cls, val)
def _convert(cls, value):
return cls(value)
_convert = classmethod(_convert)
def _string(cls, value):
value = root_frequency / value
return '%f' % value
_string = classmethod(_string)
class MemoryBandwidth(float,ParamType):
_cpp_param_decl = 'float'
def __new__(self, value):
val = toMemoryBandwidth(value)
return super(cls, MemoryBandwidth).__new__(cls, val)
def _convert(cls, value):
return cls(value)
_convert = classmethod(_convert)
def _string(cls, value):
value = root_frequency / value
return '%f' % value
_string = classmethod(_string)
# Some memory range specifications use this as a default upper bound.
MaxAddr = Addr.max
@@ -1518,6 +1590,6 @@ __all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam',
'Int32', 'UInt32', 'Int64', 'UInt64',
'Counter', 'Addr', 'Tick', 'Percent',
'MemorySize', 'RootFrequency', 'Frequency', 'Latency',
'ClockPeriod',
'ClockPeriod', 'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory', 'NULL',
'NextEthernetAddr', 'instantiate']

2
python/m5/objects/BaseCPU.mpy
View File

@@ -23,3 +23,5 @@ simobj BaseCPU(SimObject):
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
cycle_time = Param.ClockPeriod(parent.frequency, "clock speed")

2
python/m5/objects/BaseCache.mpy
View File

@@ -10,7 +10,7 @@ simobj BaseCache(BaseMem):
block_size = Param.Int("block size in bytes")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Int(0,
compression_latency = Param.Latency('0c',
"Latency in cycles of compression algorithm")
do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")

2
python/m5/objects/BaseSystem.mpy
View File

@@ -1,6 +1,8 @@
simobj BaseSystem(SimObject):
type = 'BaseSystem'
abstract = True
boot_cpu_frequency = Param.ClockPeriod(parent.cpu[0].cycle_time,
"Boot Processor Frequency")
memctrl = Param.MemoryController(parent.any, "memory controller")
physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
kernel = Param.String("file that contains the kernel code")

39
python/m5/objects/Ethernet.mpy
View File

@@ -10,16 +10,15 @@ simobj EtherLink(SimObject):
type = 'EtherLink'
int1 = Param.EtherInt("interface 1")
int2 = Param.EtherInt("interface 2")
delay = Param.Tick(0, "transmit delay of packets in us")
speed = Param.Tick(100000000, "link speed in bits per second")
delay = Param.Latency('0us', "packet transmit delay")
speed = Param.NetworkBandwidth('100Mbps', "link speed")
dump = Param.EtherDump(NULL, "dump object")
simobj EtherBus(SimObject):
type = 'EtherBus'
loopback = Param.Bool(True,
"send packet back to the interface from which it came")
loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.UInt64(100000000, "bus speed in bits per second")
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
simobj EtherTap(EtherInt):
type = 'EtherTap'
@@ -38,16 +37,16 @@ simobj EtherDev(DmaDevice):
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
intr_delay = Param.Latency('0us', "Interrupt Delay")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
tlaser = Param.Turbolaser(parent.any, "Turbolaser")
@@ -57,21 +56,23 @@ simobj NSGigE(PciDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")
rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")

2
python/m5/objects/Ide.mpy
View File

@@ -4,7 +4,7 @@ class IdeID(Enum): vals = ['master', 'slave']
simobj IdeDisk(SimObject):
type = 'IdeDisk'
delay = Param.Tick(1, "Fixed disk delay in microseconds")
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(parent.any, "Physical memory")

1
python/m5/objects/Platform.mpy
View File

@@ -1,5 +1,4 @@
simobj Platform(SimObject):
type = 'Platform'
abstract = True
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(parent.any, "interrupt controller")

2
python/m5/objects/Tsunami.mpy
View File

@@ -5,7 +5,6 @@ simobj Tsunami(Platform):
type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(parent.any, "system")
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
type = 'TsunamiCChip'
@@ -19,6 +18,7 @@ simobj TsunamiIO(FooPioDevice):
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(parent.any, "Tsunami")
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
simobj TsunamiPChip(FooPioDevice):
type = 'TsunamiPChip'