arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

src/cpu/exec_context.hh

@@ -49,6 +49,7 @@
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/static_inst_fwd.hh"
 #include "cpu/translation.hh"
 #include "mem/request.hh"
@@ -286,9 +287,9 @@ class ExecContext {
      */
 
 #if THE_ISA == MIPS_ISA
-    virtual MiscReg readRegOtherThread(int regIdx,
+    virtual MiscReg readRegOtherThread(RegId reg,
                                        ThreadID tid = InvalidThreadID) = 0;
-    virtual void setRegOtherThread(int regIdx, MiscReg val,
+    virtual void setRegOtherThread(RegId reg, MiscReg val,
                                    ThreadID tid = InvalidThreadID) = 0;
 #endif