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arch, cpu: Architectural Register structural indexing

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Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
This commit is contained in:
Nathanael Premillieu
2017-04-05 12:46:06 -05:00
committed by Andreas Sandberg
parent 864f87f9c5
commit 5e8287d2e2
70 changed files with 854 additions and 790 deletions
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2
src/arch/alpha/isa/branch.isa
View File

@@ -130,7 +130,7 @@ output decoder {{
Jump::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
uint64_t Rb = tc->readIntReg(_srcRegIdx[0].regIdx);
pc.set((Rb & ~3) | (pc.pc() & 1));
return pc;
}

2
src/arch/alpha/isa/fp.isa
View File

@@ -149,7 +149,7 @@ output decoder {{
#ifndef SS_COMPATIBLE_DISASSEMBLY
std::string suffix("");
suffix += ((_destRegIdx[0] >= FP_Reg_Base)
suffix += ((_destRegIdx[0].regClass == FloatRegClass)
? fpTrappingModeSuffix[trappingMode]
: intTrappingModeSuffix[trappingMode]);
suffix += roundingModeSuffix[roundingMode];

17
src/arch/alpha/isa/main.isa
View File

@@ -220,13 +220,6 @@ output header {{
{
protected:
/// Make AlphaISA register dependence tags directly visible in
/// this class and derived classes. Maybe these should really
/// live here and not in the AlphaISA namespace.
enum DependenceTags {
FP_Reg_Base = AlphaISA::FP_Reg_Base
};
/// Constructor.
AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
@@ -236,7 +229,7 @@ output header {{
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void printReg(std::ostream &os, int reg) const;
void printReg(std::ostream &os, RegId reg) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -251,13 +244,13 @@ output header {{
output decoder {{
void
AlphaStaticInst::printReg(std::ostream &os, int reg) const
AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
{
if (reg < FP_Reg_Base) {
ccprintf(os, "r%d", reg);
if (reg.regClass == IntRegClass) {
ccprintf(os, "r%d", reg.regIdx);
}
else {
ccprintf(os, "f%d", reg - FP_Reg_Base);
ccprintf(os, "f%d", reg.regIdx);
}
}

12
src/arch/alpha/registers.hh
View File

@@ -33,6 +33,7 @@
#include "arch/alpha/generated/max_inst_regs.hh"
#include "arch/alpha/ipr.hh"
#include "arch/generic/types.hh"
#include "base/types.hh"
namespace AlphaISA {
@@ -43,7 +44,6 @@ using AlphaISAInst::MaxInstDestRegs;
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
typedef uint8_t RegIndex;
typedef uint64_t IntReg;
// floating point register file entry type
@@ -100,16 +100,6 @@ const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs =
NumIntRegs + NumFloatRegs + NumMiscRegs;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
FP_Reg_Base = NumIntRegs,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
};
} // namespace AlphaISA
#endif // __ARCH_ALPHA_REGFILE_HH__

8
src/arch/arm/insts/branch64.cc
View File

@@ -95,7 +95,7 @@ BranchReg64::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -106,7 +106,7 @@ BranchRet64::generateDisassembly(
std::stringstream ss;
printMnemonic(ss, "", false);
if (op1 != INTREG_X30)
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -125,7 +125,7 @@ BranchImmReg64::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printTarget(ss, pc + imm, symtab);
return ss.str();
@@ -137,7 +137,7 @@ BranchImmImmReg64::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%#x, ", imm1);
printTarget(ss, pc + imm2, symtab);
return ss.str();

46
src/arch/arm/insts/data64.cc
View File

@@ -56,7 +56,7 @@ DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -84,9 +84,9 @@ DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -95,9 +95,9 @@ DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -107,9 +107,9 @@ DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d, #%d", imm1, imm2);
return ss.str();
}
@@ -119,11 +119,11 @@ DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
return ss.str();
}
@@ -132,11 +132,11 @@ DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -146,13 +146,13 @@ DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", ");
printReg(ss, op3);
printIntReg(ss, op3);
return ss.str();
}
@@ -162,7 +162,7 @@ DataXCondCompImmOp::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d, #%d", imm, defCc);
ccprintf(ss, ", ");
printCondition(ss, condCode, true);
@@ -175,9 +175,9 @@ DataXCondCompRegOp::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", #%d", defCc);
ccprintf(ss, ", ");
printCondition(ss, condCode, true);
@@ -190,11 +190,11 @@ DataXCondSelOp::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", ");
printCondition(ss, condCode, true);
return ss.str();

34
src/arch/arm/insts/macromem.cc
View File

@@ -1525,9 +1525,9 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
printIntReg(ss, ura);
ss << ", ";
printReg(ss, urb);
printIntReg(ss, urb);
ss << ", ";
ccprintf(ss, "#%d", imm);
return ss.str();
@@ -1538,9 +1538,9 @@ MicroIntImmXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
printIntReg(ss, ura);
ss << ", ";
printReg(ss, urb);
printIntReg(ss, urb);
ss << ", ";
ccprintf(ss, "#%d", imm);
return ss.str();
@@ -1560,9 +1560,9 @@ MicroIntRegXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
printIntReg(ss, ura);
ccprintf(ss, ", ");
printReg(ss, urb);
printIntReg(ss, urb);
printExtendOperand(false, ss, (IntRegIndex)urc, type, shiftAmt);
return ss.str();
}
@@ -1572,9 +1572,9 @@ MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
printIntReg(ss, ura);
ss << ", ";
printReg(ss, urb);
printIntReg(ss, urb);
return ss.str();
}
@@ -1583,11 +1583,11 @@ MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, ura);
printIntReg(ss, ura);
ss << ", ";
printReg(ss, urb);
printIntReg(ss, urb);
ss << ", ";
printReg(ss, urc);
printIntReg(ss, urc);
return ss.str();
}
@@ -1597,11 +1597,11 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::stringstream ss;
printMnemonic(ss);
if (isFloating())
printReg(ss, ura + FP_Reg_Base);
printFloatReg(ss, ura);
else
printReg(ss, ura);
printIntReg(ss, ura);
ss << ", [";
printReg(ss, urb);
printIntReg(ss, urb);
ss << ", ";
ccprintf(ss, "#%d", imm);
ss << "]";
@@ -1613,11 +1613,11 @@ MicroMemPairOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ",";
printReg(ss, dest2);
printIntReg(ss, dest2);
ss << ", [";
printReg(ss, urb);
printIntReg(ss, urb);
ss << ", ";
ccprintf(ss, "#%d", imm);
ss << "]";

14
src/arch/arm/insts/mem.cc
View File

@@ -54,7 +54,7 @@ MemoryReg::printOffset(std::ostream &os) const
{
if (!add)
os << "-";
printReg(os, index);
printIntReg(os, index);
if (shiftType != LSL || shiftAmt != 0) {
switch (shiftType) {
case LSL:
@@ -82,11 +82,11 @@ Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ss << ", [";
printReg(ss, base);
printIntReg(ss, base);
ss << "]";
return ss.str();
}
@@ -109,7 +109,7 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
printMnemonic(ss, "ib");
break;
}
printReg(ss, base);
printIntReg(ss, base);
if (wb) {
ss << "!";
}
@@ -134,7 +134,7 @@ SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
printMnemonic(ss, "ib");
break;
}
printReg(ss, INTREG_SP);
printIntReg(ss, INTREG_SP);
if (wb) {
ss << "!";
}
@@ -180,7 +180,7 @@ Memory::printInst(std::ostream &os, AddrMode addrMode) const
printMnemonic(os);
printDest(os);
os << ", [";
printReg(os, base);
printIntReg(os, base);
if (addrMode != AddrMd_PostIndex) {
os << ", ";
printOffset(os);

10
src/arch/arm/insts/mem.hh
View File

@@ -211,7 +211,7 @@ class Memory : public MightBeMicro
virtual void
printDest(std::ostream &os) const
{
printReg(os, dest);
printIntReg(os, dest);
}
void printInst(std::ostream &os, AddrMode addrMode) const;
@@ -253,7 +253,7 @@ class MemoryExImm : public MemoryImm
void
printDest(std::ostream &os) const
{
printReg(os, result);
printIntReg(os, result);
os << ", ";
MemoryImm::printDest(os);
}
@@ -277,7 +277,7 @@ class MemoryDImm : public MemoryImm
{
MemoryImm::printDest(os);
os << ", ";
printReg(os, dest2);
printIntReg(os, dest2);
}
};
@@ -296,7 +296,7 @@ class MemoryExDImm : public MemoryDImm
void
printDest(std::ostream &os) const
{
printReg(os, result);
printIntReg(os, result);
os << ", ";
MemoryDImm::printDest(os);
}
@@ -341,7 +341,7 @@ class MemoryDReg : public MemoryReg
{
MemoryReg::printDest(os);
os << ", ";
printReg(os, dest2);
printIntReg(os, dest2);
}
};

28
src/arch/arm/insts/mem64.cc
View File

@@ -54,7 +54,7 @@ SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::stringstream ss;
printMnemonic(ss, "", false);
ccprintf(ss, ", [");
printReg(ss, base);
printIntReg(ss, base);
ccprintf(ss, "]");
return ss.str();
}
@@ -65,9 +65,9 @@ void
Memory64::startDisassembly(std::ostream &os) const
{
printMnemonic(os, "", false);
printReg(os, dest);
printIntReg(os, dest);
ccprintf(os, ", [");
printReg(os, base);
printIntReg(os, base);
}
void
@@ -100,11 +100,11 @@ MemoryDImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, dest2);
printIntReg(ss, dest2);
ccprintf(ss, ", [");
printReg(ss, base);
printIntReg(ss, base);
if (imm)
ccprintf(ss, ", #%d", imm);
ccprintf(ss, "]");
@@ -116,13 +116,13 @@ MemoryDImmEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, result);
printIntReg(ss, result);
ccprintf(ss, ", ");
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, dest2);
printIntReg(ss, dest2);
ccprintf(ss, ", [");
printReg(ss, base);
printIntReg(ss, base);
if (imm)
ccprintf(ss, ", #%d", imm);
ccprintf(ss, "]");
@@ -173,11 +173,11 @@ MemoryEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, result);
printIntReg(ss, result);
ccprintf(ss, ", [");
printReg(ss, base);
printIntReg(ss, base);
ccprintf(ss, "]");
return ss.str();
}
@@ -187,7 +187,7 @@ MemoryLiteral64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", #%d", pc + imm);
return ss.str();
}

86
src/arch/arm/insts/misc.cc
View File

@@ -47,21 +47,20 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
RegIndex idx = srcRegIdx(i);
RegIndex rel_idx;
if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
RegId reg = srcRegIdx(i);
if (reg.regClass != MiscRegClass) {
continue;
}
if (rel_idx == MISCREG_CPSR) {
if (reg.regIdx == MISCREG_CPSR) {
ss << "cpsr";
foundPsr = true;
break;
}
if (rel_idx == MISCREG_SPSR) {
if (reg.regIdx == MISCREG_SPSR) {
ss << "spsr";
foundPsr = true;
break;
@@ -80,17 +79,16 @@ MsrBase::printMsrBase(std::ostream &os) const
bool apsr = false;
bool foundPsr = false;
for (unsigned i = 0; i < numDestRegs(); i++) {
int idx = destRegIdx(i);
if (idx < Misc_Reg_Base) {
RegId reg = destRegIdx(i);
if (reg.regClass != MiscRegClass) {
continue;
}
idx -= Misc_Reg_Base;
if (idx == MISCREG_CPSR) {
if (reg.regIdx == MISCREG_CPSR) {
os << "cpsr_";
foundPsr = true;
break;
}
if (idx == MISCREG_SPSR) {
if (reg.regIdx == MISCREG_SPSR) {
if (bits(byteMask, 1, 0)) {
os << "spsr_";
} else {
@@ -142,7 +140,7 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::stringstream ss;
printMsrBase(ss);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -151,11 +149,11 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, dest2);
printIntReg(ss, dest2);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -164,11 +162,11 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ss << ", ";
printReg(ss, op2);
printIntReg(ss, op2);
return ss.str();
}
@@ -186,7 +184,7 @@ RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -196,9 +194,9 @@ RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -207,11 +205,11 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ss << ", ";
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -221,13 +219,13 @@ RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ss << ", ";
printReg(ss, op2);
printIntReg(ss, op2);
ss << ", ";
printReg(ss, op3);
printIntReg(ss, op3);
return ss.str();
}
@@ -236,11 +234,11 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ss << ", ";
printReg(ss, op2);
printIntReg(ss, op2);
return ss.str();
}
@@ -249,9 +247,9 @@ RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -261,9 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -273,9 +271,9 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -285,7 +283,7 @@ RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", #%d, #%d", imm1, imm2);
return ss.str();
}
@@ -295,9 +293,9 @@ RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d, #%d", imm1, imm2);
return ss.str();
}
@@ -307,9 +305,9 @@ RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", #%d, ", imm);
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}
@@ -318,10 +316,10 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", #%d, ", imm);
printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
printReg(ss, op1);
printIntReg(ss, op1);
return ss.str();
}

10
src/arch/arm/insts/misc64.cc
View File

@@ -44,9 +44,9 @@ RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", #%d, #%d", imm1, imm2);
return ss.str();
}
@@ -57,11 +57,11 @@ RegRegRegImmOp64::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ss << ", ";
printReg(ss, op1);
printIntReg(ss, op1);
ss << ", ";
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", #%d", imm);
return ss.str();
}

100
src/arch/arm/insts/static_inst.cc
View File

@@ -291,54 +291,56 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
return 0;
}
void
ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const
{
if (aarch64) {
if (reg_idx == INTREG_UREG0)
ccprintf(os, "ureg0");
else if (reg_idx == INTREG_SPX)
ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
else if (reg_idx == INTREG_X31)
ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
else
ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg_idx);
} else {
switch (reg_idx) {
case PCReg:
ccprintf(os, "pc");
break;
case StackPointerReg:
ccprintf(os, "sp");
break;
case FramePointerReg:
ccprintf(os, "fp");
break;
case ReturnAddressReg:
ccprintf(os, "lr");
break;
default:
ccprintf(os, "r%d", reg_idx);
break;
}
}
}
void
ArmStaticInst::printReg(std::ostream &os, int reg) const
ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
{
RegIndex rel_reg;
ccprintf(os, "f%d", reg_idx);
}
switch (regIdxToClass(reg, &rel_reg)) {
case IntRegClass:
if (aarch64) {
if (reg == INTREG_UREG0)
ccprintf(os, "ureg0");
else if (reg == INTREG_SPX)
ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
else if (reg == INTREG_X31)
ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
else
ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg);
} else {
switch (rel_reg) {
case PCReg:
ccprintf(os, "pc");
break;
case StackPointerReg:
ccprintf(os, "sp");
break;
case FramePointerReg:
ccprintf(os, "fp");
break;
case ReturnAddressReg:
ccprintf(os, "lr");
break;
default:
ccprintf(os, "r%d", reg);
break;
}
}
break;
case FloatRegClass:
ccprintf(os, "f%d", rel_reg);
break;
case MiscRegClass:
assert(rel_reg < NUM_MISCREGS);
ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
break;
case CCRegClass:
ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
break;
}
void
ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
{
ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
}
void
ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
{
assert(reg_idx < NUM_MISCREGS);
ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
}
void
@@ -471,7 +473,7 @@ ArmStaticInst::printShiftOperand(std::ostream &os,
bool firstOp = false;
if (rm != INTREG_ZERO) {
printReg(os, rm);
printIntReg(os, rm);
}
bool done = false;
@@ -520,7 +522,7 @@ ArmStaticInst::printShiftOperand(std::ostream &os,
if (immShift)
os << "#" << shiftAmt;
else
printReg(os, rs);
printIntReg(os, rs);
}
}
@@ -531,7 +533,7 @@ ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
{
if (!firstOperand)
ccprintf(os, ", ");
printReg(os, rm);
printIntReg(os, rm);
if (type == UXTX && shiftAmt == 0)
return;
switch (type) {
@@ -568,7 +570,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
// Destination
if (rd != INTREG_ZERO) {
firstOp = false;
printReg(os, rd);
printIntReg(os, rd);
}
// Source 1.
@@ -576,7 +578,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
if (!firstOp)
os << ", ";
firstOp = false;
printReg(os, rn);
printIntReg(os, rn);
}
if (!firstOp)

5
src/arch/arm/insts/static_inst.hh
View File

@@ -155,7 +155,10 @@ class ArmStaticInst : public StaticInst
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void printReg(std::ostream &os, int reg) const;
void printIntReg(std::ostream &os, RegIndex reg_idx) const;
void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
void printCCReg(std::ostream &os, RegIndex reg_idx) const;
void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
void printMnemonic(std::ostream &os,
const std::string &suffix = "",
bool withPred = true,

46
src/arch/arm/insts/vfp.cc
View File

@@ -51,9 +51,9 @@ FpCondCompRegOp::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", #%d", defCc);
ccprintf(ss, ", ");
printCondition(ss, condCode, true);
@@ -66,11 +66,11 @@ FpCondSelOp::generateDisassembly(
{
std::stringstream ss;
printMnemonic(ss, "", false);
printReg(ss, dest);
printIntReg(ss, dest);
ccprintf(ss, ", ");
printReg(ss, op1);
printIntReg(ss, op1);
ccprintf(ss, ", ");
printReg(ss, op2);
printIntReg(ss, op2);
ccprintf(ss, ", ");
printCondition(ss, condCode, true);
return ss.str();
@@ -81,9 +81,9 @@ FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ss << ", ";
printReg(ss, op1 + FP_Reg_Base);
printFloatReg(ss, op1);
return ss.str();
}
@@ -92,7 +92,7 @@ FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -102,9 +102,9 @@ FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ss << ", ";
printReg(ss, op1 + FP_Reg_Base);
printFloatReg(ss, op1);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -114,11 +114,11 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ss << ", ";
printReg(ss, op1 + FP_Reg_Base);
printFloatReg(ss, op1);
ss << ", ";
printReg(ss, op2 + FP_Reg_Base);
printFloatReg(ss, op2);
return ss.str();
}
@@ -129,11 +129,11 @@ FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab)
std::stringstream ss;
printMnemonic(ss);
printCondition(ss, cond);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ss << ", ";
printReg(ss, op1 + FP_Reg_Base);
printFloatReg(ss, op1);
ss << ", ";
printReg(ss, op2 + FP_Reg_Base);
printFloatReg(ss, op2);
return ss.str();
}
@@ -142,13 +142,13 @@ FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ss << ", ";
printReg(ss, op1 + FP_Reg_Base);
printFloatReg(ss, op1);
ss << ", ";
printReg(ss, op2 + FP_Reg_Base);
printFloatReg(ss, op2);
ss << ", ";
printReg(ss, op3 + FP_Reg_Base);
printFloatReg(ss, op3);
return ss.str();
}
@@ -157,11 +157,11 @@ FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest + FP_Reg_Base);
printFloatReg(ss, dest);
ss << ", ";
printReg(ss, op1 + FP_Reg_Base);
printFloatReg(ss, op1);
ss << ", ";
printReg(ss, op2 + FP_Reg_Base);
printFloatReg(ss, op2);
ccprintf(ss, ", #%d", imm);
return ss.str();
}

8
src/arch/arm/registers.hh
View File

@@ -58,8 +58,6 @@ const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
using ArmISAInst::MaxInstDestRegs;
using ArmISAInst::MaxMiscDestRegs;
typedef uint16_t RegIndex;
typedef uint64_t IntReg;
// floating point register file entry type
@@ -109,12 +107,6 @@ const int SyscallNumReg = ReturnValueReg;
const int SyscallPseudoReturnReg = ReturnValueReg;
const int SyscallSuccessReg = ReturnValueReg;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
IntReg intreg;
FloatReg fpreg;

3
src/arch/generic/types.hh
View File

@@ -37,6 +37,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
// Logical register index type.
typedef uint16_t RegIndex;
namespace GenericISA
{

40
src/arch/isa_parser.py
View File

@@ -520,7 +520,14 @@ class Operand(object):
# to avoid 'uninitialized variable' errors from the compiler.
return self.ctype + ' ' + self.base_name + ' = 0;\n';
src_reg_constructor = '\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s);'
dst_reg_constructor = '\n\t_destRegIdx[_numDestRegs++] = RegId(%s, %s);'
class IntRegOperand(Operand):
reg_class = 'IntRegClass'
def isReg(self):
return 1
@@ -532,14 +539,13 @@ class IntRegOperand(Operand):
c_dest = ''
if self.is_src:
c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s;' % (self.reg_spec)
c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
if self.hasReadPred():
c_src = '\n\tif (%s) {%s\n\t}' % \
(self.read_predicate, c_src)
if self.is_dest:
c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s;' % \
(self.reg_spec)
c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += '\n\t_numIntDestRegs++;'
if self.hasWritePred():
c_dest = '\n\tif (%s) {%s\n\t}' % \
@@ -592,6 +598,8 @@ class IntRegOperand(Operand):
return wb
class FloatRegOperand(Operand):
reg_class = 'FloatRegClass'
def isReg(self):
return 1
@@ -603,13 +611,10 @@ class FloatRegOperand(Operand):
c_dest = ''
if self.is_src:
c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Reg_Base;' % \
(self.reg_spec)
c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
if self.is_dest:
c_dest = \
'\n\t_destRegIdx[_numDestRegs++] = %s + FP_Reg_Base;' % \
(self.reg_spec)
c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += '\n\t_numFPDestRegs++;'
return c_src + c_dest
@@ -654,6 +659,8 @@ class FloatRegOperand(Operand):
return wb
class CCRegOperand(Operand):
reg_class = 'CCRegClass'
def isReg(self):
return 1
@@ -665,16 +672,13 @@ class CCRegOperand(Operand):
c_dest = ''
if self.is_src:
c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + CC_Reg_Base;' % \
(self.reg_spec)
c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
if self.hasReadPred():
c_src = '\n\tif (%s) {%s\n\t}' % \
(self.read_predicate, c_src)
if self.is_dest:
c_dest = \
'\n\t_destRegIdx[_numDestRegs++] = %s + CC_Reg_Base;' % \
(self.reg_spec)
c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += '\n\t_numCCDestRegs++;'
if self.hasWritePred():
c_dest = '\n\tif (%s) {%s\n\t}' % \
@@ -727,6 +731,8 @@ class CCRegOperand(Operand):
return wb
class ControlRegOperand(Operand):
reg_class = 'MiscRegClass'
def isReg(self):
return 1
@@ -738,14 +744,10 @@ class ControlRegOperand(Operand):
c_dest = ''
if self.is_src:
c_src = \
'\n\t_srcRegIdx[_numSrcRegs++] = %s + Misc_Reg_Base;' % \
(self.reg_spec)
c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
if self.is_dest:
c_dest = \
'\n\t_destRegIdx[_numDestRegs++] = %s + Misc_Reg_Base;' % \
(self.reg_spec)
c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
return c_src + c_dest

10
src/arch/mips/isa/base.isa
View File

@@ -53,7 +53,7 @@ output header {{
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void printReg(std::ostream &os, int reg) const;
void printReg(std::ostream &os, RegId reg) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -70,13 +70,13 @@ output header {{
//Ouputs to decoder.cc
output decoder {{
void MipsStaticInst::printReg(std::ostream &os, int reg) const
void MipsStaticInst::printReg(std::ostream &os, RegId reg) const
{
if (reg < FP_Reg_Base) {
ccprintf(os, "r%d", reg);
if (reg.regClass == IntRegClass) {
ccprintf(os, "r%d", reg.regIdx);
}
else {
ccprintf(os, "f%d", reg - FP_Reg_Base);
ccprintf(os, "f%d", reg.regIdx);
}
}

181
src/arch/mips/isa/decoder.isa
View File

@@ -384,44 +384,86 @@ decode OPCODE_HI default Unknown::unknown() {
// Decode MIPS MT MFTR instruction into sub-instructions
0x8: decode MT_U {
0x0: mftc0({{
data = xc->readRegOtherThread((RT << 3 | SEL) +
Misc_Reg_Base);
data = xc->readRegOtherThread(RegId(MiscRegClass,
(RT << 3 | SEL)));
}});
0x1: decode SEL {
0x0: mftgpr({{
data = xc->readRegOtherThread(RT);
data = xc->readRegOtherThread(
RegId(IntRegClass, RT));
}});
0x1: decode RT {
0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
0x0: mftlo_dsp0({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO0));
}});
0x1: mfthi_dsp0({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI0));
}});
0x2: mftacx_dsp0({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX0));
}});
0x4: mftlo_dsp1({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO1));
}});
0x5: mfthi_dsp1({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI1));
}});
0x6: mftacx_dsp1({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX1));
}});
0x8: mftlo_dsp2({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO2));
}});
0x9: mfthi_dsp2({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI2));
}});
0x10: mftacx_dsp2({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX2));
}});
0x12: mftlo_dsp3({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO3));
}});
0x13: mfthi_dsp3({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI3));
}});
0x14: mftacx_dsp3({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX3));
}});
0x16: mftdsp({{
data = xc->readRegOtherThread(
RegId(IntRegClass, INTREG_DSP_CONTROL));
}});
default: CP0Unimpl::unknown();
}
0x2: decode MT_H {
0x0: mftc1({{ data = xc->readRegOtherThread(RT +
FP_Reg_Base);
0x0: mftc1({{
data = xc->readRegOtherThread(
RegId(FloatRegClass, RT));
}});
0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
FP_Reg_Base);
0x1: mfthc1({{
data = xc->readRegOtherThread(
RegId(FloatRegClass, RT));
}});
}
0x3: cftc1({{
uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
FP_Reg_Base);
uint32_t fcsr_val = xc->readRegOtherThread(
RegId(FloatRegClass, FLOATREG_FCSR));
switch (RT) {
case 0:
data = xc->readRegOtherThread(FLOATREG_FIR +
Misc_Reg_Base);
data = xc->readRegOtherThread(
RegId(MiscRegClass, FLOATREG_FIR));
break;
case 25:
data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,56 +492,62 @@ decode OPCODE_HI default Unknown::unknown() {
format MT_MTTR {
// Decode MIPS MT MTTR instruction into sub-instructions
0xC: decode MT_U {
0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
Rt);
0x0: mttc0({{ xc->setRegOtherThread(
RegId(MiscRegClass, (RD << 3 | SEL)), Rt);
}});
0x1: decode SEL {
0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
0x0: mttgpr({{ xc->setRegOtherThread(
RegId(IntRegClass, RD), Rt);
}});
0x1: decode RT {
0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
}});
0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
Rt);
}});
0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
Rt);
}});
0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
Rt);
}});
0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
Rt);
}});
0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
Rt);
}});
0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
Rt);
}});
0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
Rt);
}});
0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
Rt);
}});
0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
Rt);
}});
0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
Rt);
}});
0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
}});
0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
0x0: mttlo_dsp0({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO0), Rt);
}});
0x1: mtthi_dsp0({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI0), Rt);
}});
0x2: mttacx_dsp0({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX0), Rt);
}});
0x4: mttlo_dsp1({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO1), Rt);
}});
0x5: mtthi_dsp1({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI1), Rt);
}});
0x6: mttacx_dsp1({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX1), Rt);
}});
0x8: mttlo_dsp2({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO2), Rt);
}});
0x9: mtthi_dsp2({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI2), Rt);
}});
0x10: mttacx_dsp2({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX2), Rt);
}});
0x12: mttlo_dsp3({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_LO3), Rt);
}});
0x13: mtthi_dsp3({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_HI3), Rt);
}});
0x14: mttacx_dsp3({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_ACX3), Rt);
}});
0x16: mttdsp({{ xc->setRegOtherThread(
RegId(IntRegClass, INTREG_DSP_CONTROL), Rt);
}});
default: CP0Unimpl::unknown();
}
0x2: mttc1({{
uint64_t data = xc->readRegOtherThread(RD +
FP_Reg_Base);
uint64_t data = xc->readRegOtherThread(
RegId(FloatRegClass, RD));
data = insertBits(data, MT_H ? 63 : 31,
MT_H ? 32 : 0, Rt);
xc->setRegOtherThread(RD + FP_Reg_Base,
xc->setRegOtherThread(RegId(FloatRegClass, RD),
data);
}});
0x3: cttc1({{
@@ -534,7 +582,8 @@ decode OPCODE_HI default Unknown::unknown() {
"Access to Floating Control "
"S""tatus Register", FS);
}
xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
xc->setRegOtherThread(
RegId(FloatRegClass, FLOATREG_FCSR), data);
}});
default: CP0Unimpl::unknown();
}

12
src/arch/mips/isa/formats/int.isa
View File

@@ -257,9 +257,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
} else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -272,9 +272,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
} else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -287,9 +287,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
} else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}

3
src/arch/mips/isa/formats/mt.isa
View File

@@ -102,7 +102,8 @@ output exec {{
MVPConf0Reg &mvp_conf0)
{
vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass,
MISCREG_TC_BIND));
tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);

23
src/arch/mips/mt.hh
View File

@@ -113,24 +113,25 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
int success = 0;
for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
TCBindReg tidTCBind =
tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND), tid);
TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
if (tidTCBind.curVPE == tcBind.curVPE) {
TCStatusReg tidTCStatus =
tc->readRegOtherThread(MISCREG_TC_STATUS +
Misc_Reg_Base,tid);
tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS),
tid);
TCHaltReg tidTCHalt =
tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT),
tid);
if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
tidTCStatus.a == 0 && success == 0) {
tc->setRegOtherThread(MISCREG_TC_RESTART +
Misc_Reg_Base, Rs, tid);
tc->setRegOtherThread(Rd_bits, Rt, tid);
tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_RESTART),
Rs, tid);
tc->setRegOtherThread(RegId(IntRegClass, Rd_bits), Rt, tid);
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS);
@@ -149,7 +150,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
tidTCStatus.asid = tcStatus.asid;
// Write Status Register
tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS),
tidTCStatus, tid);
// Mark As Successful Fork
@@ -185,13 +186,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
for (ThreadID tid = 0; tid < num_threads; tid++) {
TCStatusReg tidTCStatus =
tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS),
tid);
TCHaltReg tidTCHalt =
tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT),
tid);
TCBindReg tidTCBind =
tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND),
tid);
if (tidTCBind.curVPE == tcBind.curVPE &&

8
src/arch/mips/registers.hh
View File

@@ -275,16 +275,8 @@ enum MiscRegIndex{
const int NumMiscRegs = MISCREG_NUMREGS;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
typedef uint16_t RegIndex;
typedef uint32_t IntReg;
// floating point register file entry type

2
src/arch/null/registers.hh
View File

@@ -40,6 +40,7 @@
#ifndef __ARCH_NULL_REGISTERS_HH__
#define __ARCH_NULL_REGISTERS_HH__
#include "arch/types.hh"
#include "base/types.hh"
namespace NullISA {
@@ -49,6 +50,7 @@ typedef uint32_t FloatRegBits;
typedef float FloatReg;
typedef uint8_t CCReg;
typedef uint64_t MiscReg;
const RegIndex ZeroReg = 0;
}

2
src/arch/power/insts/branch.cc
View File

@@ -153,7 +153,7 @@ BranchNonPCRelCond::generateDisassembly(Addr pc,
PowerISA::PCState
BranchRegCond::branchTarget(ThreadContext *tc) const
{
uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]);
uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx);
return regVal & 0xfffffffc;
}

12
src/arch/power/insts/static_inst.cc
View File

@@ -36,19 +36,17 @@
using namespace PowerISA;
void
PowerStaticInst::printReg(std::ostream &os, int reg) const
PowerStaticInst::printReg(std::ostream &os, RegId reg) const
{
RegIndex rel_reg;
switch (regIdxToClass(reg, &rel_reg)) {
switch (reg.regClass) {
case IntRegClass:
ccprintf(os, "r%d", rel_reg);
ccprintf(os, "r%d", reg.regIdx);
break;
case FloatRegClass:
ccprintf(os, "f%d", rel_reg);
ccprintf(os, "f%d", reg.regIdx);
break;
case MiscRegClass:
switch (rel_reg) {
switch (reg.regIdx) {
case 0: ccprintf(os, "cr"); break;
case 1: ccprintf(os, "xer"); break;
case 2: ccprintf(os, "lr"); break;

2
src/arch/power/insts/static_inst.hh
View File

@@ -59,7 +59,7 @@ class PowerStaticInst : public StaticInst
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void
printReg(std::ostream &os, int reg) const;
printReg(std::ostream &os, RegId reg) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;

8
src/arch/power/registers.hh
View File

@@ -43,8 +43,6 @@ using PowerISAInst::MaxInstDestRegs;
// be detected by it. Manually add it here.
const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
typedef uint8_t RegIndex;
typedef uint64_t IntReg;
// Floating point register file entry type
@@ -87,12 +85,6 @@ const int SyscallNumReg = 0;
const int SyscallPseudoReturnReg = 3;
const int SyscallSuccessReg = 3;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
IntReg intreg;
FloatReg fpreg;

15
src/arch/riscv/isa/base.isa
View File

@@ -51,7 +51,7 @@ output header {{
{}
std::string
regName(RegIndex reg) const;
regName(RegId reg) const;
virtual std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
@@ -68,12 +68,15 @@ output header {{
//Ouputs to decoder.cc
output decoder {{
std::string
RiscvStaticInst::regName(RegIndex reg) const
RiscvStaticInst::regName(RegId reg) const
{
if (reg < FP_Reg_Base) {
return std::string(RegisterNames[reg]);
} else {
return std::string("f") + std::to_string(reg - FP_Reg_Base);
switch (reg.regClass) {
case IntRegClass:
return std::string(RegisterNames[reg.regIdx]);
case FloatRegClass:
return std::string("f") + std::to_string(reg.regIdx);
default:
return csprintf("unknown[%i/%i]", reg.regClass, reg.regIdx);
}
}
}};

2
src/arch/riscv/isa/formats/type.isa
View File

@@ -210,7 +210,7 @@ output decoder {{
Jump::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
IntReg Rs1 = tc->readIntReg(_srcRegIdx[0]);
IntReg Rs1 = tc->readIntReg(_srcRegIdx[0].regIdx);
pc.set((Rs1 + imm)&~0x1);
return pc;
}

8
src/arch/riscv/registers.hh
View File

@@ -50,6 +50,7 @@
#include <map>
#include <string>
#include "arch/generic/types.hh"
#include "arch/isa_traits.hh"
#include "arch/riscv/generated/max_inst_regs.hh"
#include "base/types.hh"
@@ -60,7 +61,6 @@ using RiscvISAInst::MaxInstSrcRegs;
using RiscvISAInst::MaxInstDestRegs;
const int MaxMiscDestRegs = 1;
typedef uint_fast16_t RegIndex;
typedef uint64_t IntReg;
typedef uint64_t FloatRegBits;
typedef double FloatReg;
@@ -74,12 +74,6 @@ const int NumFloatRegs = 32;
const int NumCCRegs = 0;
const int NumMiscRegs = 4096;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
// Semantically meaningful register indices
const int ZeroReg = 0;
const int ReturnAddrReg = 1;

49
src/arch/sparc/isa/base.isa
View File

@@ -105,12 +105,12 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
void printReg(std::ostream &os, int reg) const;
void printReg(std::ostream &os, RegId reg) const;
void printSrcReg(std::ostream &os, int reg) const;
void printDestReg(std::ostream &os, int reg) const;
void printRegArray(std::ostream &os,
const RegIndex indexArray[], int num) const;
const RegId indexArray[], int num) const;
void advancePC(SparcISA::PCState &pcState) const;
};
@@ -251,7 +251,7 @@ output decoder {{
}
void SparcStaticInst::printRegArray(std::ostream &os,
const RegIndex indexArray[], int num) const
const RegId indexArray[], int num) const
{
if (num <= 0)
return;
@@ -283,35 +283,36 @@ output decoder {{
}
void
SparcStaticInst::printReg(std::ostream &os, int reg) const
SparcStaticInst::printReg(std::ostream &os, RegId reg) const
{
const int MaxGlobal = 8;
const int MaxOutput = 16;
const int MaxLocal = 24;
const int MaxInput = 32;
const int MaxMicroReg = 40;
if (reg < FP_Reg_Base) {
RegIndex reg_idx = reg.regIdx;
if (reg.regClass == IntRegClass) {
// If we used a register from the next or previous window,
// take out the offset.
while (reg >= MaxMicroReg)
reg -= MaxMicroReg;
if (reg == FramePointerReg)
while (reg_idx >= MaxMicroReg)
reg_idx -= MaxMicroReg;
if (reg_idx == FramePointerReg)
ccprintf(os, "%%fp");
else if (reg == StackPointerReg)
else if (reg_idx == StackPointerReg)
ccprintf(os, "%%sp");
else if (reg < MaxGlobal)
ccprintf(os, "%%g%d", reg);
else if (reg < MaxOutput)
ccprintf(os, "%%o%d", reg - MaxGlobal);
else if (reg < MaxLocal)
ccprintf(os, "%%l%d", reg - MaxOutput);
else if (reg < MaxInput)
ccprintf(os, "%%i%d", reg - MaxLocal);
else if (reg < MaxMicroReg)
ccprintf(os, "%%u%d", reg - MaxInput);
else if (reg_idx < MaxGlobal)
ccprintf(os, "%%g%d", reg_idx);
else if (reg_idx < MaxOutput)
ccprintf(os, "%%o%d", reg_idx - MaxGlobal);
else if (reg_idx < MaxLocal)
ccprintf(os, "%%l%d", reg_idx - MaxOutput);
else if (reg_idx < MaxInput)
ccprintf(os, "%%i%d", reg_idx - MaxLocal);
else if (reg_idx < MaxMicroReg)
ccprintf(os, "%%u%d", reg_idx - MaxInput);
// The fake int regs that are really control regs
else {
switch (reg - MaxMicroReg) {
switch (reg_idx - MaxMicroReg) {
case 1:
ccprintf(os, "%%y");
break;
@@ -335,10 +336,10 @@ output decoder {{
break;
}
}
} else if (reg < Misc_Reg_Base) {
ccprintf(os, "%%f%d", reg - FP_Reg_Base);
} else if (reg.regClass == FloatRegClass) {
ccprintf(os, "%%f%d", reg_idx);
} else {
switch (reg - Misc_Reg_Base) {
switch (reg_idx) {
case MISCREG_ASI:
ccprintf(os, "%%asi");
break;
@@ -430,7 +431,7 @@ output decoder {{
ccprintf(os, "%%fsr");
break;
default:
ccprintf(os, "%%ctrl%d", reg - Misc_Reg_Base);
ccprintf(os, "%%ctrl%d", reg_idx);
}
}
}

4
src/arch/sparc/isa/formats/integerop.isa
View File

@@ -155,7 +155,7 @@ output decoder {{
IntOp::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const
{
if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) {
if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].regIdx == 0) {
printMnemonic(os, "mov");
printSrcReg(os, 1);
ccprintf(os, ", ");
@@ -170,7 +170,7 @@ output decoder {{
const SymbolTable *symbab) const
{
if (!std::strcmp(mnemonic, "or")) {
if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) {
if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx == 0) {
if (imm == 0) {
printMnemonic(os, "clr");
} else {

4
src/arch/sparc/isa/formats/mem/util.isa
View File

@@ -84,7 +84,7 @@ output decoder {{
ccprintf(response, ", ");
}
ccprintf(response, "[");
if (_srcRegIdx[!store ? 0 : 1] != 0) {
if (_srcRegIdx[!store ? 0 : 1].regIdx != 0) {
printSrcReg(response, !store ? 0 : 1);
ccprintf(response, " + ");
}
@@ -111,7 +111,7 @@ output decoder {{
ccprintf(response, ", ");
}
ccprintf(response, "[");
if (_srcRegIdx[!save ? 0 : 1] != 0) {
if (_srcRegIdx[!save ? 0 : 1].regIdx != 0) {
printReg(response, _srcRegIdx[!save ? 0 : 1]);
ccprintf(response, " + ");
}

4
src/arch/sparc/isa/formats/priv.isa
View File

@@ -155,7 +155,7 @@ output decoder {{
ccprintf(response, " ");
// If the first reg is %g0, don't print it.
// This improves readability
if (_srcRegIdx[0] != 0) {
if (_srcRegIdx[0].regIdx != 0) {
printSrcReg(response, 0);
ccprintf(response, ", ");
}
@@ -175,7 +175,7 @@ output decoder {{
ccprintf(response, " ");
// If the first reg is %g0, don't print it.
// This improves readability
if (_srcRegIdx[0] != 0) {
if (_srcRegIdx[0].regIdx != 0) {
printSrcReg(response, 0);
ccprintf(response, ", ");
}

10
src/arch/sparc/registers.hh
View File

@@ -59,8 +59,6 @@ typedef union
MiscReg ctrlreg;
} AnyReg;
typedef uint16_t RegIndex;
// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
// the rest of these depend on the ABI
@@ -78,14 +76,6 @@ const int NumCCRegs = 0;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
FP_Reg_Base = NumIntRegs,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs,
};
} // namespace SparcISA
#endif

2
src/arch/x86/insts/microfpop.hh
View File

@@ -66,7 +66,7 @@ namespace X86ISA
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), src2(_src2.idx), dest(_dest.idx),
src1(_src1.regIdx), src2(_src2.regIdx), dest(_dest.regIdx),
dataSize(_dataSize), spm(_spm)
{}
/*

14
src/arch/x86/insts/microldstop.hh
View File

@@ -75,12 +75,12 @@ namespace X86ISA
Request::FlagsType _memFlags,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags, __opClass),
scale(_scale), index(_index.idx), base(_base.idx),
disp(_disp), segment(_segment.idx),
scale(_scale), index(_index.regIdx), base(_base.regIdx),
disp(_disp), segment(_segment.regIdx),
dataSize(_dataSize), addressSize(_addressSize),
memFlags(_memFlags | _segment.idx)
memFlags(_memFlags | _segment.regIdx)
{
assert(_segment.idx < NUM_SEGMENTREGS);
assert(_segment.regIdx < NUM_SEGMENTREGS);
foldOBit =
(dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
foldABit =
@@ -110,7 +110,7 @@ namespace X86ISA
_scale, _index, _base, _disp, _segment,
_dataSize, _addressSize, _memFlags,
__opClass),
data(_data.idx)
data(_data.regIdx)
{
}
@@ -143,8 +143,8 @@ namespace X86ISA
_scale, _index, _base, _disp, _segment,
_dataSize, _addressSize, _memFlags,
__opClass),
dataLow(_dataLow.idx),
dataHi(_dataHi.idx)
dataLow(_dataLow.regIdx),
dataHi(_dataHi.regIdx)
{
}

4
src/arch/x86/insts/micromediaop.hh
View File

@@ -59,7 +59,7 @@ namespace X86ISA
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), dest(_dest.idx),
src1(_src1.regIdx), dest(_dest.regIdx),
srcSize(_srcSize), destSize(_destSize), ext(_ext)
{}
@@ -102,7 +102,7 @@ namespace X86ISA
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
src2(_src2.idx)
src2(_src2.regIdx)
{}
std::string generateDisassembly(Addr pc,

4
src/arch/x86/insts/microregop.hh
View File

@@ -64,7 +64,7 @@ namespace X86ISA
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), dest(_dest.idx),
src1(_src1.regIdx), dest(_dest.regIdx),
dataSize(_dataSize), ext(_ext)
{
foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
@@ -90,7 +90,7 @@ namespace X86ISA
RegOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _dataSize, _ext,
__opClass),
src2(_src2.idx)
src2(_src2.regIdx)
{
}

48
src/arch/x86/insts/static_inst.cc
View File

@@ -120,7 +120,7 @@ namespace X86ISA
}
void
X86StaticInst::printReg(std::ostream &os, int reg, int size) const
X86StaticInst::printReg(std::ostream &os, RegId reg, int size) const
{
assert(size == 1 || size == 2 || size == 4 || size == 8);
static const char * abcdFormats[9] =
@@ -132,20 +132,20 @@ namespace X86ISA
static const char * microFormats[9] =
{"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
RegIndex rel_reg;
RegIndex reg_idx = reg.regIdx;
switch (regIdxToClass(reg, &rel_reg)) {
switch (reg.regClass) {
case IntRegClass: {
const char * suffix = "";
bool fold = rel_reg & IntFoldBit;
rel_reg &= ~IntFoldBit;
bool fold = reg_idx & IntFoldBit;
reg_idx &= ~IntFoldBit;
if (fold)
suffix = "h";
else if (rel_reg < 8 && size == 1)
else if (reg_idx < 8 && size == 1)
suffix = "l";
switch (rel_reg) {
switch (reg_idx) {
case INTREG_RAX:
ccprintf(os, abcdFormats[size], "a");
break;
@@ -195,41 +195,41 @@ namespace X86ISA
ccprintf(os, longFormats[size], "15");
break;
default:
ccprintf(os, microFormats[size], rel_reg - NUM_INTREGS);
ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
}
ccprintf(os, suffix);
break;
}
case FloatRegClass: {
if (rel_reg < NumMMXRegs) {
ccprintf(os, "%%mmx%d", rel_reg);
if (reg_idx < NumMMXRegs) {
ccprintf(os, "%%mmx%d", reg_idx);
return;
}
rel_reg -= NumMMXRegs;
if (rel_reg < NumXMMRegs * 2) {
ccprintf(os, "%%xmm%d_%s", rel_reg / 2,
(rel_reg % 2) ? "high": "low");
reg_idx -= NumMMXRegs;
if (reg_idx < NumXMMRegs * 2) {
ccprintf(os, "%%xmm%d_%s", reg_idx / 2,
(reg_idx % 2) ? "high": "low");
return;
}
rel_reg -= NumXMMRegs * 2;
if (rel_reg < NumMicroFpRegs) {
ccprintf(os, "%%ufp%d", rel_reg);
reg_idx -= NumXMMRegs * 2;
if (reg_idx < NumMicroFpRegs) {
ccprintf(os, "%%ufp%d", reg_idx);
return;
}
rel_reg -= NumMicroFpRegs;
ccprintf(os, "%%st(%d)", rel_reg);
reg_idx -= NumMicroFpRegs;
ccprintf(os, "%%st(%d)", reg_idx);
break;
}
case CCRegClass:
ccprintf(os, "%%cc%d", rel_reg);
ccprintf(os, "%%cc%d", reg_idx);
break;
case MiscRegClass:
switch (rel_reg) {
switch (reg_idx) {
default:
ccprintf(os, "%%ctrl%d", rel_reg);
ccprintf(os, "%%ctrl%d", reg_idx);
}
break;
}
@@ -250,14 +250,14 @@ namespace X86ISA
{
if (scale != 1)
ccprintf(os, "%d*", scale);
printReg(os, index, addressSize);
printReg(os, InstRegIndex(index), addressSize);
someAddr = true;
}
if (base != ZeroReg)
{
if (someAddr)
os << " + ";
printReg(os, base, addressSize);
printReg(os, InstRegIndex(base), addressSize);
someAddr = true;
}
}

32
src/arch/x86/insts/static_inst.hh
View File

@@ -51,11 +51,27 @@ namespace X86ISA
* wrapper struct for these lets take advantage of the compiler's type
* checking.
*/
struct InstRegIndex
struct InstRegIndex : public RegId
{
RegIndex idx;
explicit InstRegIndex(RegIndex _idx) : idx(_idx)
{}
explicit InstRegIndex(RegIndex _idx) :
RegId(computeRegClass(_idx), _idx) {}
private:
// TODO: As X86 register index definition is highly built on the
// unified space concept, it is easier for the moment to rely on
// an helper function to compute the RegClass. It would be nice
// to fix those definition and get rid of this.
RegClass computeRegClass(RegIndex _idx) {
if (_idx < FP_Reg_Base) {
return IntRegClass;
} else if (_idx < CC_Reg_Base) {
return FloatRegClass;
} else if (_idx < Misc_Reg_Base) {
return CCRegClass;
} else {
return MiscRegClass;
}
}
};
/**
@@ -81,7 +97,7 @@ namespace X86ISA
void printSegment(std::ostream &os, int segment) const;
void printReg(std::ostream &os, int reg, int size) const;
void printReg(std::ostream &os, RegId reg, int size) const;
void printSrcReg(std::ostream &os, int reg, int size) const;
void printDestReg(std::ostream &os, int reg, int size) const;
void printMem(std::ostream &os, uint8_t segment,
@@ -91,7 +107,7 @@ namespace X86ISA
inline uint64_t merge(uint64_t into, uint64_t val, int size) const
{
X86IntReg reg = into;
if (_destRegIdx[0] & IntFoldBit)
if (_destRegIdx[0].regIdx & IntFoldBit)
{
reg.H = val;
return reg;
@@ -122,7 +138,7 @@ namespace X86ISA
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
if (_srcRegIdx[idx] & IntFoldBit)
if (_srcRegIdx[idx].regIdx & IntFoldBit)
return reg.H;
switch(size)
{
@@ -143,7 +159,7 @@ namespace X86ISA
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
if (_srcRegIdx[idx] & IntFoldBit)
if (_srcRegIdx[idx].regIdx & IntFoldBit)
return reg.SH;
switch(size)
{

2
src/arch/x86/isa/microops/limmop.isa
View File

@@ -95,7 +95,7 @@ def template MicroLimmOpConstructor {{
InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
setFlags, %(op_class)s),
dest(_dest.idx), imm(_imm), dataSize(_dataSize)
dest(_dest.regIdx), imm(_imm), dataSize(_dataSize)
{
foldOBit = (dataSize == 1 && !machInst.rex.present) ? 1 << 6 : 0;
%(constructor)s;

25
src/arch/x86/isa/specialize.isa
View File

@@ -143,13 +143,19 @@ let {{
regString = "INTREG_R%s" % opType.reg
env.addReg(regString)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % regString)
"printReg(out, InstRegIndex(%s), regSize);\n" %
regString)
Name += "_R"
elif opType.tag == "B":
# This refers to registers whose index is encoded as part of the opcode
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % InstRegIndex)
"printReg(out, InstRegIndex(%s), regSize);\n" %
InstRegIndex)
Name += "_R"
env.addReg(InstRegIndex)
elif opType.tag == "M":
# This refers to memory. The macroop constructor sets up modrm
@@ -182,8 +188,11 @@ let {{
# Use the "reg" field of the ModRM byte to select the register
env.addReg(ModRMRegIndex)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRegIndex)
"printReg(out, InstRegIndex(%s), regSize);\n" %
ModRMRegIndex)
if opType.tag == "P":
Name += "_MMX"
elif opType.tag == "V":
Name += "_XMM"
@@ -195,8 +204,11 @@ let {{
regEnv = copy.copy(env)
regEnv.addReg(ModRMRMIndex)
regEnv.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRMIndex)
"printReg(out, InstRegIndex(%s), regSize);\n" %
ModRMRMIndex)
# This refers to memory. The macroop constructor should set up
# modrm addressing.
memEnv = copy.copy(env)
memEnv.doModRM = True
@@ -222,8 +234,11 @@ let {{
# Non register modrm settings should cause an error
env.addReg(ModRMRMIndex)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRMIndex)
"printReg(out, InstRegIndex(%s), regSize);\n" %
ModRMRMIndex)
if opType.tag == "PR":
Name += "_MMX"
elif opType.tag == "VR":
Name += "_XMM"

2
src/arch/x86/registers.hh
View File

@@ -105,8 +105,6 @@ typedef union
MiscReg ctrlReg;
} AnyReg;
typedef uint16_t RegIndex;
} // namespace X86ISA
#endif // __ARCH_X86_REGFILE_HH__