From 5e3226bed53d44906520530bf062b42cbb83d15a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 26 Oct 2021 22:02:13 -0700 Subject: [PATCH] arch,sim: Add a byteOrder accessor to the Workload class. The workload would have a better idea of what it's endianness is than the system object that holds it. This is the first step towards getting rid of the getByteOrder method on the system object, which currently checks TARGET_ISA to determine what the default endianness should be. If it makes sense for a Workload, it could determine the endianness dynamically by, for instance, reading it out of a binary image before putting it into memory. This does assume that the workload has a consistent endianness throughout which may not be true, but this is not a new assumption. Also, mark the SEWorkload SimObject class as "abstract", since it isn't useful until they get subclassed by some arch specific version. Change-Id: I8d4ba8382f22236a81f9738cc3506cdb97bdbfb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52104 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/freebsd/se_workload.hh | 2 ++ src/arch/arm/fs_workload.hh | 2 ++ src/arch/arm/linux/se_workload.hh | 1 + src/arch/mips/linux/se_workload.hh | 1 + src/arch/power/linux/se_workload.hh | 2 ++ src/arch/riscv/bare_metal/fs_workload.hh | 1 + src/arch/riscv/linux/fs_workload.hh | 2 ++ src/arch/riscv/linux/se_workload.hh | 2 ++ src/arch/sparc/fs_workload.hh | 1 + src/arch/sparc/linux/se_workload.hh | 1 + src/arch/x86/fs_workload.hh | 2 ++ src/arch/x86/linux/se_workload.hh | 1 + src/sim/Workload.py | 3 +++ src/sim/kernel_workload.hh | 1 + src/sim/workload.hh | 3 +++ 15 files changed, 25 insertions(+) diff --git a/src/arch/arm/freebsd/se_workload.hh b/src/arch/arm/freebsd/se_workload.hh index a7f34532d2..8069bd2563 100644 --- a/src/arch/arm/freebsd/se_workload.hh +++ b/src/arch/arm/freebsd/se_workload.hh @@ -55,6 +55,8 @@ class EmuFreebsd : public SEWorkload EmuFreebsd(const Params &p) : SEWorkload(p, PageShift) {} + ByteOrder byteOrder() const override { return ByteOrder::little; } + struct BaseSyscallABI {}; struct SyscallABI32 : public SEWorkload::SyscallABI32, public BaseSyscallABI diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh index c917ffd05b..547bbf1e70 100644 --- a/src/arch/arm/fs_workload.hh +++ b/src/arch/arm/fs_workload.hh @@ -143,6 +143,8 @@ class FsWorkload : public KernelWorkload return loader::Arm64; } + ByteOrder byteOrder() const override { return ByteOrder::little; } + FsWorkload(const Params &p); void initState() override; diff --git a/src/arch/arm/linux/se_workload.hh b/src/arch/arm/linux/se_workload.hh index 0ff08c7d74..b22688fb8e 100644 --- a/src/arch/arm/linux/se_workload.hh +++ b/src/arch/arm/linux/se_workload.hh @@ -47,6 +47,7 @@ class EmuLinux : public SEWorkload using Params = ArmEmuLinuxParams; EmuLinux(const Params &p) : SEWorkload(p, PageShift) {} + ByteOrder byteOrder() const override { return ByteOrder::little; } struct BaseSyscallABI {}; struct SyscallABI32 : public SEWorkload::SyscallABI32, diff --git a/src/arch/mips/linux/se_workload.hh b/src/arch/mips/linux/se_workload.hh index c94112c335..7e4d863f35 100644 --- a/src/arch/mips/linux/se_workload.hh +++ b/src/arch/mips/linux/se_workload.hh @@ -51,6 +51,7 @@ class EmuLinux : public SEWorkload using Params = MipsEmuLinuxParams; EmuLinux(const Params &p) : SEWorkload(p, PageShift) {} + ByteOrder byteOrder() const override { return ByteOrder::little; } void syscall(ThreadContext *tc) override; }; diff --git a/src/arch/power/linux/se_workload.hh b/src/arch/power/linux/se_workload.hh index 1b380adc7e..192147edf1 100644 --- a/src/arch/power/linux/se_workload.hh +++ b/src/arch/power/linux/se_workload.hh @@ -53,6 +53,8 @@ class EmuLinux : public SEWorkload EmuLinux(const Params &p) : SEWorkload(p, PageShift) {} + ByteOrder byteOrder() const override { return ByteOrder::big; } + void syscall(ThreadContext *tc) override; }; diff --git a/src/arch/riscv/bare_metal/fs_workload.hh b/src/arch/riscv/bare_metal/fs_workload.hh index 875910ad86..e10c0a0433 100644 --- a/src/arch/riscv/bare_metal/fs_workload.hh +++ b/src/arch/riscv/bare_metal/fs_workload.hh @@ -64,6 +64,7 @@ class BareMetal : public Workload } loader::Arch getArch() const override { return bootloader->getArch(); } + ByteOrder byteOrder() const override { return ByteOrder::little; } const loader::SymbolTable & symtab(ThreadContext *tc) override diff --git a/src/arch/riscv/linux/fs_workload.hh b/src/arch/riscv/linux/fs_workload.hh index f85ec16e7a..cb29beeafc 100644 --- a/src/arch/riscv/linux/fs_workload.hh +++ b/src/arch/riscv/linux/fs_workload.hh @@ -53,6 +53,8 @@ class FsLinux : public KernelWorkload KernelWorkload::setSystem(sys); gdb = BaseRemoteGDB::build(system); } + + ByteOrder byteOrder() const override { return ByteOrder::little; } }; } // namespace RiscvISA diff --git a/src/arch/riscv/linux/se_workload.hh b/src/arch/riscv/linux/se_workload.hh index bdc39ceb14..41a3d41f61 100644 --- a/src/arch/riscv/linux/se_workload.hh +++ b/src/arch/riscv/linux/se_workload.hh @@ -57,6 +57,8 @@ class EmuLinux : public SEWorkload EmuLinux(const Params &p) : SEWorkload(p, PageShift) {} + ByteOrder byteOrder() const override { return ByteOrder::little; } + void syscall(ThreadContext *tc) override; }; diff --git a/src/arch/sparc/fs_workload.hh b/src/arch/sparc/fs_workload.hh index 06f02cf4ad..90d5131a21 100644 --- a/src/arch/sparc/fs_workload.hh +++ b/src/arch/sparc/fs_workload.hh @@ -64,6 +64,7 @@ class FsWorkload : public Workload return pc; } loader::Arch getArch() const override { return loader::SPARC64; } + ByteOrder byteOrder() const override { return ByteOrder::big; } const loader::SymbolTable & symtab(ThreadContext *tc) override diff --git a/src/arch/sparc/linux/se_workload.hh b/src/arch/sparc/linux/se_workload.hh index 01ab9b7253..72bad471a0 100644 --- a/src/arch/sparc/linux/se_workload.hh +++ b/src/arch/sparc/linux/se_workload.hh @@ -58,6 +58,7 @@ class EmuLinux : public SEWorkload EmuLinux(const Params &p); loader::Arch getArch() const override { return loader::SPARC64; } + ByteOrder byteOrder() const override { return ByteOrder::big; } void handleTrap(ThreadContext *tc, int trapNum) override; void syscall(ThreadContext *tc) override; diff --git a/src/arch/x86/fs_workload.hh b/src/arch/x86/fs_workload.hh index 6c2038f017..779e6ab577 100644 --- a/src/arch/x86/fs_workload.hh +++ b/src/arch/x86/fs_workload.hh @@ -91,6 +91,8 @@ class FsWorkload : public KernelWorkload gdb = BaseRemoteGDB::build(system); } + ByteOrder byteOrder() const override { return ByteOrder::little; } + protected: smbios::SMBiosTable *smbiosTable; diff --git a/src/arch/x86/linux/se_workload.hh b/src/arch/x86/linux/se_workload.hh index 76db91f42d..85b0d69814 100644 --- a/src/arch/x86/linux/se_workload.hh +++ b/src/arch/x86/linux/se_workload.hh @@ -68,6 +68,7 @@ class EmuLinux : public SEWorkload } loader::Arch getArch() const override { return loader::X86_64; } + ByteOrder byteOrder() const override { return ByteOrder::little; } void syscall(ThreadContext *tc) override; void event(ThreadContext *tc) override; diff --git a/src/sim/Workload.py b/src/sim/Workload.py index 8d6316435d..bd1a230071 100644 --- a/src/sim/Workload.py +++ b/src/sim/Workload.py @@ -43,6 +43,8 @@ class StubWorkload(Workload): cxx_class = 'gem5::StubWorkload' entry = Param.Addr(0, 'Dummy entry point for this workload.') + byte_order = Param.ByteOrder('little', + 'Dummy byte order for this workload.') class KernelWorkload(Workload): type = 'KernelWorkload' @@ -74,6 +76,7 @@ class SEWorkload(Workload, metaclass=SEWorkloadMeta): type = 'SEWorkload' cxx_header = "sim/se_workload.hh" cxx_class = 'gem5::SEWorkload' + abstract = True @classmethod def _is_compatible_with(cls, obj): diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh index a1e8b98e4a..503e6ea81a 100644 --- a/src/sim/kernel_workload.hh +++ b/src/sim/kernel_workload.hh @@ -84,6 +84,7 @@ class KernelWorkload : public Workload KernelWorkload(const Params &p); Addr getEntry() const override { return kernelObj->entryPoint(); } + ByteOrder byteOrder() const override { return kernelObj->getByteOrder(); } loader::Arch getArch() const override { diff --git a/src/sim/workload.hh b/src/sim/workload.hh index c09c56c2f0..9b3ef04fb7 100644 --- a/src/sim/workload.hh +++ b/src/sim/workload.hh @@ -33,6 +33,7 @@ #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" +#include "enums/ByteOrder.hh" #include "params/StubWorkload.hh" #include "params/Workload.hh" #include "sim/sim_object.hh" @@ -98,6 +99,7 @@ class Workload : public SimObject void startup() override; virtual Addr getEntry() const = 0; + virtual ByteOrder byteOrder() const = 0; virtual loader::Arch getArch() const = 0; virtual const loader::SymbolTable &symtab(ThreadContext *tc) = 0; @@ -170,6 +172,7 @@ class StubWorkload : public Workload StubWorkload(const StubWorkloadParams ¶ms) : Workload(params) {} Addr getEntry() const override { return params().entry; } + ByteOrder byteOrder() const override { return params().byte_order; } loader::Arch getArch() const override { return loader::UnknownArch; } const loader::SymbolTable & symtab(ThreadContext *tc) override