diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 32d18adab2..f00e2868da 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -77,4 +77,11 @@ class AbstractMemory(ClockedObject):
 
     writeable = Param.Bool(True, "Allow writes to this memory")
 
-    collect_stats = Param.Bool(True, "Collect traffic statistics")
+    collect_stats = Param.Bool(
+        True,
+        "Collect statistics per requestor for "
+        "each type of access. Set this to `False` if "
+        "requestors may be unknown or when running "
+        "with multiple `System` objects without a "
+        "`SysBridge`.",
+    )
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index f22ea35527..461fd4c1fe 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -433,8 +433,9 @@ AbstractMemory::access(PacketPtr pkt)
 
             assert(!pkt->req->isInstFetch());
             TRACE_PACKET("Read/Write");
-            if (collectStats)
+            if (collectStats) {
                 stats.numOther[pkt->req->requestorId()]++;
+            }
         }
     } else if (pkt->isRead()) {
         assert(!pkt->isWrite());
@@ -451,8 +452,9 @@ AbstractMemory::access(PacketPtr pkt)
         if (collectStats) {
             stats.numReads[pkt->req->requestorId()]++;
             stats.bytesRead[pkt->req->requestorId()] += pkt->getSize();
-            if (pkt->req->isInstFetch())
+            if (pkt->req->isInstFetch()) {
                 stats.bytesInstRead[pkt->req->requestorId()] += pkt->getSize();
+            }
         }
     } else if (pkt->isInvalidate() || pkt->isClean()) {
         assert(!pkt->isWrite());