diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index f66171a95a..3f123405e9 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -38,11 +38,37 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import Enum
+from m5.params import Enum, UInt32
 from m5.params import Param
 from m5.objects.BaseISA import BaseISA
 
 
+class RiscvVectorLength(UInt32):
+    min = 8
+    max = 65536
+
+    def _check(self):
+        super()._check()
+
+        # VLEN needs to be a whole power of 2. We already know value is
+        # not zero. Hence:
+        if self.value & (self.value - 1) != 0:
+            raise TypeError("VLEN is not a power of 2: %d" % self.value)
+
+
+class RiscvVectorElementLength(UInt32):
+    min = 8
+    max = 64
+
+    def _check(self):
+        super()._check()
+
+        # ELEN needs to be a whole power of 2. We already know value is
+        # not zero. Hence:
+        if self.value & (self.value - 1) != 0:
+            raise TypeError("ELEN is not a power of 2: %d" % self.value)
+
+
 class RiscvType(Enum):
     vals = ["RV32", "RV64"]
 
@@ -58,3 +84,13 @@ class RiscvISA(BaseISA):
     riscv_type = Param.RiscvType("RV64", "RV32 or RV64")
 
     enable_rvv = Param.Bool(True, "Enable vector extension")
+    vlen = Param.RiscvVectorLength(
+        256,
+        "Length of each vector register in bits. \
+        VLEN in Ch. 2 of RISC-V vector spec",
+    )
+    elen = Param.RiscvVectorElementLength(
+        64,
+        "Length of each vector element in bits. \
+        ELEN in Ch. 2 of RISC-V vector spec",
+    )
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a1f4056bf5..5785a14e92 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -36,6 +36,7 @@
 #include <sstream>
 
 #include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/static_inst.hh"
 #include "arch/riscv/interrupts.hh"
 #include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable.hh"
@@ -253,10 +254,9 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 
 } // anonymous namespace
 
-ISA::ISA(const Params &p) :
-    BaseISA(p), _rvType(p.riscv_type), checkAlignment(p.check_alignment),
-    enableRvv(p.enable_rvv)
-
+ISA::ISA(const Params &p) :BaseISA(p),
+    _rvType(p.riscv_type), checkAlignment(p.check_alignment),
+    enableRvv(p.enable_rvv),vlen(p.vlen),elen(p.elen)
 {
     _regClasses.push_back(&intRegClass);
     _regClasses.push_back(&floatRegClass);
@@ -267,6 +267,11 @@ ISA::ISA(const Params &p) :
     _regClasses.push_back(&ccRegClass);
     _regClasses.push_back(&miscRegClass);
 
+    fatal_if( p.vlen < p.elen,
+    "VLEN should be greater or equal",
+        "than ELEN. Ch. 2RISC-V vector spec.");
+
+
     miscRegFile.resize(NUM_MISCREGS);
     clear();
 }
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 13366ef4c3..5581c3b677 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -84,6 +84,16 @@ class ISA : public BaseISA
     const Addr INVALID_RESERVATION_ADDR = (Addr)-1;
     std::unordered_map<int, Addr> load_reservation_addrs;
 
+    /** Length of each vector register in bits.
+     *  VLEN in Ch. 2 of RISC-V vector spec
+     */
+    unsigned vlen;
+
+    /** Length of each vector element in bits.
+     *  ELEN in Ch. 2 of RISC-V vector spec
+    */
+    unsigned elen;
+
   public:
     using Params = RiscvISAParams;
 
@@ -92,7 +102,8 @@ class ISA : public BaseISA
     PCStateBase*
     newPCState(Addr new_inst_addr=0) const override
     {
-        return new PCState(new_inst_addr, _rvType, VLENB);
+        unsigned vlenb = vlen >> 3;
+        return new PCState(new_inst_addr, _rvType, vlenb);
     }
 
   public:
@@ -147,6 +158,10 @@ class ISA : public BaseISA
         Addr& load_reservation_addr = load_reservation_addrs[cid];
         load_reservation_addr = INVALID_RESERVATION_ADDR;
     }
+    /** Methods for getting VLEN, VLENB and ELEN values */
+    unsigned getVecLenInBits() { return vlen; }
+    unsigned getVecLenInBytes() { return vlen >> 3; }
+    unsigned getVecElemLenInBits() { return elen; }
 };
 
 } // namespace RiscvISA
diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh
index 918e85708b..03a7fc415f 100644
--- a/src/arch/riscv/pcstate.hh
+++ b/src/arch/riscv/pcstate.hh
@@ -62,7 +62,7 @@ class PCState : public GenericISA::UPCState<4>
 
     bool _compressed = false;
     RiscvType _rvType = RV64;
-    uint64_t _vlenb = VLENB;
+    uint64_t _vlenb = 256;
     VTYPE _vtype = (1ULL << 63); // vtype.vill = 1 at initial;
     uint32_t _vl = 0;
 
@@ -74,7 +74,7 @@ class PCState : public GenericISA::UPCState<4>
     PCState &operator=(const PCState &other) = default;
     PCState() = default;
     explicit PCState(Addr addr) { set(addr); }
-    explicit PCState(Addr addr, RiscvType rvType, uint64_t vlenb = VLENB)
+    explicit PCState(Addr addr, RiscvType rvType, uint64_t vlenb)
     {
         set(addr);
         _rvType = rvType;