From 5cfad84a988bd3df7dedbfb858eb69906b22eaf9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sa=C3=BAl?= <33020671+saul44203@users.noreply.github.com> Date: Sat, 8 Jun 2024 07:33:56 +0200 Subject: [PATCH] arch-riscv: correctly set dynamic VLEN for all arith instructions (#1187) Some arithmetic instructions of the riscv vector extension where still using the default VLEN=256 instead of the dynamic one through the inherited `vlen` attribute. Most of them only use this to calculate the effective index for the mask element like so: ``` uint32_t ei = i + vtype_VLMAX(vtype, vlen, true) * this->microIdx; if (this->vm || elem_mask(v0, ei)) { ... ``` This means that instructions will wrongly compute the mask index in the second and subsequent micro instructions (`microIdx` > 0). This commit fixes this by adding the corresponding `set_vlen` snippet to the affected instruction formats. Change-Id: Ib041de972d6938490741a9fb4c214a6a5172c34e --- src/arch/riscv/isa/formats/vector_arith.isa | 12 ++++++++++++ src/arch/riscv/isa/templates/vector_arith.isa | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/src/arch/riscv/isa/formats/vector_arith.isa b/src/arch/riscv/isa/formats/vector_arith.isa index 453ef3a04c..3b7a57e208 100644 --- a/src/arch/riscv/isa/formats/vector_arith.isa +++ b/src/arch/riscv/isa/formats/vector_arith.isa @@ -209,6 +209,7 @@ def format VectorIntFormat(code, category, *flags) {{ vm_decl_rd = vmDeclAndReadData() set_vlenb = setVlenb() + set_vlen = setVlen() if need_elem_idx else "" microiop = InstObjParams(name + "_micro", Name + "Micro", @@ -217,6 +218,7 @@ def format VectorIntFormat(code, category, *flags) {{ 'set_dest_reg_idx': set_dest_reg_idx, 'set_src_reg_idx': set_src_reg_idx, 'set_vlenb' : set_vlenb, + 'set_vlen' : set_vlen, 'vm_decl_rd': vm_decl_rd, 'copy_old_vd': copyOldVd(old_vd_idx), 'declare_varith_template': declareVArithTemplate(Name + "Micro")}, @@ -484,6 +486,7 @@ def format VectorIntMaskFormat(code, category, *flags) {{ vm_decl_rd = vmDeclAndReadData() set_vlenb = setVlenb() + set_vlen = setVlen() if need_elem_idx else "" microiop = InstObjParams(name + "_micro", Name + "Micro", @@ -492,6 +495,7 @@ def format VectorIntMaskFormat(code, category, *flags) {{ 'set_dest_reg_idx': set_dest_reg_idx, 'set_src_reg_idx': set_src_reg_idx, 'set_vlenb': set_vlenb, + 'set_vlen': set_vlen, 'vm_decl_rd': vm_decl_rd, 'copy_old_vd': copyOldVd(old_vd_idx), 'declare_varith_template': declareVArithTemplate(Name + "Micro")}, @@ -620,6 +624,7 @@ def format VectorFloatFormat(code, category, *flags) {{ vm_decl_rd = vmDeclAndReadData() set_vlenb = setVlenb(); + set_vlen = setVlen() if need_elem_idx else "" varith_micro_declare = declareVArithTemplate(Name + "Micro", 'float', 16) microiop = InstObjParams(name + "_micro", @@ -629,6 +634,7 @@ def format VectorFloatFormat(code, category, *flags) {{ 'set_dest_reg_idx': set_dest_reg_idx, 'set_src_reg_idx': set_src_reg_idx, 'set_vlenb': set_vlenb, + 'set_vlen': set_vlen, 'vm_decl_rd': vm_decl_rd, 'copy_old_vd': copyOldVd(2), 'declare_varith_template': varith_micro_declare}, @@ -673,6 +679,7 @@ def format VectorFloatCvtFormat(code, category, *flags) {{ vm_decl_rd = vmDeclAndReadData() set_vlenb = setVlenb(); + set_vlen = setVlen() varith_micro_declare = declareVArithTemplate(Name + "Micro", 'float', 16) microiop = InstObjParams(name + "_micro", @@ -682,6 +689,7 @@ def format VectorFloatCvtFormat(code, category, *flags) {{ 'set_dest_reg_idx': set_dest_reg_idx, 'set_src_reg_idx': set_src_reg_idx, 'set_vlenb': set_vlenb, + 'set_vlen': set_vlen, 'vm_decl_rd': vm_decl_rd, 'copy_old_vd': copyOldVd(old_vd_idx), 'declare_varith_template': varith_micro_declare}, @@ -919,6 +927,7 @@ def format VectorFloatMaskFormat(code, category, *flags) {{ set_src_reg_idx += setSrcVm() vm_decl_rd = vmDeclAndReadData() set_vlenb = setVlenb() + set_vlen = setVlen() code = maskCondWrapper(code) code = eiDeclarePrefix(code) @@ -933,6 +942,7 @@ def format VectorFloatMaskFormat(code, category, *flags) {{ 'set_dest_reg_idx': set_dest_reg_idx, 'set_src_reg_idx': set_src_reg_idx, 'set_vlenb': set_vlenb, + 'set_vlen': set_vlen, 'vm_decl_rd': vm_decl_rd, 'copy_old_vd': copyOldVd(2), 'declare_varith_template': varith_micro_declare}, @@ -1364,6 +1374,7 @@ def format VectorIntVxsatFormat(code, category, *flags) {{ vm_decl_rd = vmDeclAndReadData() set_vlenb = setVlenb() + set_vlen = setVlen() code = maskCondWrapper(code) code = eiDeclarePrefix(code) @@ -1376,6 +1387,7 @@ def format VectorIntVxsatFormat(code, category, *flags) {{ 'set_dest_reg_idx': set_dest_reg_idx, 'set_src_reg_idx': set_src_reg_idx, 'set_vlenb': set_vlenb, + 'set_vlen': set_vlen, 'vm_decl_rd': vm_decl_rd, 'copy_old_vd': copyOldVd(old_vd_idx), 'declare_varith_template': declareVArithTemplate(Name + "Micro")}, diff --git a/src/arch/riscv/isa/templates/vector_arith.isa b/src/arch/riscv/isa/templates/vector_arith.isa index 37bdbfe231..d000113a89 100644 --- a/src/arch/riscv/isa/templates/vector_arith.isa +++ b/src/arch/riscv/isa/templates/vector_arith.isa @@ -179,6 +179,7 @@ Fault %(op_decl)s; %(op_rd)s; %(set_vlenb)s; + %(set_vlen)s; %(vm_decl_rd)s; %(copy_old_vd)s; %(code)s; @@ -650,6 +651,7 @@ Fault %(op_decl)s; %(op_rd)s; %(set_vlenb)s; + %(set_vlen)s; %(vm_decl_rd)s; %(copy_old_vd)s; %(code)s; @@ -1224,6 +1226,7 @@ Fault %(op_decl)s; %(op_rd)s; %(set_vlenb)s; + %(set_vlen)s; %(vm_decl_rd)s; %(copy_old_vd)s; @@ -1348,6 +1351,7 @@ Fault %(op_decl)s; %(op_rd)s; %(set_vlenb)s; + %(set_vlen)s; %(vm_decl_rd)s; %(copy_old_vd)s;