diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 3598f34d01..4a0a8e3403 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -36,6 +36,9 @@
 #include "dev/arm/gic_v3_distributor.hh"
 #include "dev/arm/gic_v3_redistributor.hh"
 
+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
+
 Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
     : BaseISADevice(),
       gic(gic),
@@ -322,6 +325,8 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
                 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
             } else {
                 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
+                bpr = std::max(bpr, group == Gicv3::G1S ?
+                    GIC_MIN_BPR : GIC_MIN_BPR_NS);
             }
 
             if (sat_inc) {
@@ -1844,7 +1849,7 @@ Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
  * GroupBits() Pseudocode from spec.
  */
 uint32_t
-Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
+Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
 {
     ICC_CTLR_EL1 icc_ctlr_el1_s =
         isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
@@ -1859,9 +1864,9 @@ Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
     int bpr;
 
     if (group == Gicv3::G0S) {
-        bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
+        bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
     } else {
-        bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
+        bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7;
     }
 
     if (group == Gicv3::G1NS) {
@@ -2165,7 +2170,7 @@ Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
 }
 
 bool
-Gicv3CPUInterface::hppiCanPreempt() const
+Gicv3CPUInterface::hppiCanPreempt()
 {
     if (hppi.prio == 0xff) {
         // there is no pending interrupt
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh
index 931eb1df88..e6dcb51ff3 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -296,11 +296,11 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     uint32_t getHPPIR1() const;
     int getHPPVILR() const;
     bool groupEnabled(Gicv3::GroupId group) const;
-    uint32_t groupPriorityMask(Gicv3::GroupId group) const;
+    uint32_t groupPriorityMask(Gicv3::GroupId group);
     bool haveEL(ArmISA::ExceptionLevel el) const;
     int highestActiveGroup() const;
     uint8_t highestActivePriority() const;
-    bool hppiCanPreempt() const;
+    bool hppiCanPreempt();
     bool hppviCanPreempt(int lrIdx) const;
     bool inSecureState() const;
     ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;