arch-arm: Add matrix register support for SME

We add support for the matrix registers to the Arm architecture. This
will be used to implement support for Arm's Scalable Matrix Extension
(SME) in subsequent commits.

We add an implementation of a matrix register for the Arm
architecture. These are akin to 2D vector registers in the sense that
they can be dynamically viewed as a variety of element sizes. As
widening the element size would reduce the matrix size by a factor of
element size, we instead layer multiple tiles of wider elements onto
the underlying matrix storage in order to retain square matrices.

We separate the storage of the matrix from the different views one can
have. The potential views are:

* Tiles: View the matrix as one or more tiles using a specified
  element size. As the element size increases the number of indexable
  tiles increases. When using the smallest granularity element size
  (bytes) there is a single tile. As an example, using 32-bit elements
  yields 4 tiles. Tiles are interleaved onto the underlaying matrix
  modulo element size. A tile supports 2D indexing ([][]), with the
  first index specifying the row index, and the second the column
  (element index within the row).

* A Horizontal/Vertical slice (row or a column) of a tile: Take the
  aforementioned tile, and extract a specified row or column slice
  from it. A slice supports standard []-based indexing. A tile slice
  must use the same underlying element type as is used for the tile.

* A Horizontal/Vertical slice (row or column) of the underlying matrix
  storage: Treat the matrix register as an array of vectors (rows or
  columns, rows preferred due to them being indepependent of the
  element size being used).

On simulator start-up the matrix registers are initialised to a
maximum size. At run-time the used size can by dynamically
adjusted. However, please note that as the matrix register class
doesn't know if a smaller size is being used, the class itself doesn't
do any bounds checking itself. This is left to the user.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289

Change-Id: I6a6a05154846e4802e9822bbbac00ab2c39538ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64334
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/SConscript

@@ -54,6 +54,7 @@ if env['USE_ARM_ISA']:
           '../../cpu/reg_class.cc',
           '../../sim/bufval.cc', '../../sim/cur_tick.cc',
           'regs/int.cc')
+    GTest('matrix.test', 'matrix.test.cc')
 Source('decoder.cc', tags='arm isa')
 Source('faults.cc', tags='arm isa')
 Source('htm.cc', tags='arm isa')