diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 5e1c5ad3cd..cbbd11cf86 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -231,19 +231,6 @@ class ThreadContext : public PCEventScope
         return getReg(reg);
     }
 
-    TheISA::VecPredRegContainer
-    readVecPredReg(const RegId &reg) const
-    {
-        TheISA::VecPredRegContainer val;
-        getReg(reg, &val);
-        return val;
-    }
-    TheISA::VecPredRegContainer&
-    getWritableVecPredReg(const RegId& reg)
-    {
-        return *(TheISA::VecPredRegContainer *)getWritableReg(reg);
-    }
-
     RegVal
     readCCReg(RegIndex reg_idx) const
     {
@@ -274,12 +261,6 @@ class ThreadContext : public PCEventScope
         setReg(reg, val);
     }
 
-    void
-    setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val)
-    {
-        setReg(reg, &val);
-    }
-
     void
     setCCReg(RegIndex reg_idx, RegVal val)
     {