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system-arm: Initialize ICC_SRE_EL3 register

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Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized
before accessing other interrupt controller system registers.

Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Chun-Chen TK Hsu
2019-07-23 18:51:16 +08:00
parent a3ac8caba9
commit 5bb6210b10
1 changed files with 5 additions and 0 deletions
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5
system/arm/aarch64_bootloader/boot.S
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@@ -90,6 +90,11 @@ _start:
str w0, [x1], #4
str w0, [x1], #4
/* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
orr x10, x10, #0xf // enable 0xf
msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
isb
2: mov x0, #1
msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable