diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index ec655c1eac..5486bbcf94 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1432,6 +1432,8 @@ ISA::initializeMiscRegMetadata()
       .allPrivileges();
     InitReg(MISCREG_SEV_MAILBOX)
       .allPrivileges();
+    InitReg(MISCREG_TLBINEEDSYNC)
+      .allPrivileges().exceptUserMode();
 
     // AArch32 CP14 registers
     InitReg(MISCREG_DBGDIDR)
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index d06684ae0a..9b517a7277 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -90,6 +90,7 @@ namespace ArmISA
         MISCREG_PMXEVTYPER_PMCCFILTR,
         MISCREG_SCTLR_RST,
         MISCREG_SEV_MAILBOX,
+        MISCREG_TLBINEEDSYNC,
 
         // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
         MISCREG_DBGDIDR,
@@ -1302,6 +1303,7 @@ namespace ArmISA
         "pmxevtyper_pmccfiltr",
         "sctlr_rst",
         "sev_mailbox",
+        "tlbi_needsync",
 
         // AArch32 CP14 registers
         "dbgdidr",