From 5b0596935d46461cd8402574a8d260ef7c657ebe Mon Sep 17 00:00:00 2001 From: Laura Hinman Date: Mon, 5 Jul 2021 17:54:45 +0000 Subject: [PATCH] learning-gem5: Updated deprecated terms in simple.py Updated terms include: -`slave` is now `cpu_side_ports` -`master` is now `mem_side_ports` -`int_master` is now `int_requestor` -`int_slave` is now `int_responder` Change-Id: Ic5a0d722f3c3c529ecbdc33413b17b4f72180ef3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47639 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- configs/learning_gem5/part1/simple.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 69521fe07c..235165b5c7 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -59,8 +59,8 @@ system.cpu = TimingSimpleCPU() system.membus = SystemXBar() # Hook the CPU ports up to the membus -system.cpu.icache_port = system.membus.slave -system.cpu.dcache_port = system.membus.slave +system.cpu.icache_port = system.membus.cpu_side_ports +system.cpu.dcache_port = system.membus.cpu_side_ports # create the interrupt controller for the CPU and connect to the membus system.cpu.createInterruptController() @@ -68,18 +68,18 @@ system.cpu.createInterruptController() # For x86 only, make sure the interrupts are connected to the memory # Note: these are directly connected to the memory bus and are not cached if m5.defines.buildEnv['TARGET_ISA'] == "x86": - system.cpu.interrupts[0].pio = system.membus.master - system.cpu.interrupts[0].int_master = system.membus.slave - system.cpu.interrupts[0].int_slave = system.membus.master + system.cpu.interrupts[0].pio = system.membus.mem_side_ports + system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports + system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = MemCtrl() system.mem_ctrl.dram = DDR3_1600_8x8() system.mem_ctrl.dram.range = system.mem_ranges[0] -system.mem_ctrl.port = system.membus.master +system.mem_ctrl.port = system.membus.mem_side_ports # Connect the system up to the membus -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # get ISA for the binary to run. isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()