diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index b84aa810b0..6da8b770e1 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -983,26 +983,6 @@ ArmStaticInst::sveAccessTrap(ExceptionLevel el) const } } -Fault -ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) const -{ - const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; - - if (ArmSystem::haveVirtualization(tc) && el <= EL2) { - CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2); - if (cptrEnCheck.tz) - return sveAccessTrap(EL2); - } - - if (ArmSystem::haveSecurity(tc)) { - CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3); - if (!cptrEnCheck.ez) - return sveAccessTrap(EL3); - } - - return NoFault; -} - Fault ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const { @@ -1011,9 +991,20 @@ ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const (el == EL1 && !(cpacr.zen & 0x1))) return sveAccessTrap(EL1); - return checkSveTrap(tc, cpsr); -} + if (ArmSystem::haveVirtualization(tc) && el <= EL2) { + CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL2); + if (cptr_en_check.tz) + return sveAccessTrap(EL2); + } + if (ArmSystem::haveSecurity(tc)) { + CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3); + if (!cptr_en_check.ez) + return sveAccessTrap(EL3); + } + + return NoFault; +} static uint8_t getRestoredITBits(ThreadContext *tc, CPSR spsr) diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index ce6569a7a0..bee39036b4 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -475,11 +475,6 @@ class ArmStaticInst : public StaticInst */ Fault sveAccessTrap(ExceptionLevel el) const; - /** - * Check an SVE access against CPTR_EL2 and CPTR_EL3. - */ - Fault checkSveTrap(ThreadContext *tc, CPSR cpsr) const; - /** * Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. */