MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
This commit is contained in:
Andreas Hansson
@@ -46,7 +46,7 @@ from m5.params import *
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# There are a few things we need that aren't in params.__all__ since
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# normal users don't need them
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from m5.params import ParamDesc, VectorParamDesc, \
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isNullPointer, SimObjectVector
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isNullPointer, SimObjectVector, Port
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from m5.proxy import *
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from m5.proxy import isproxy
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@@ -1,3 +1,15 @@
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2004-2006 The Regents of The University of Michigan
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# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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# All rights reserved.
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@@ -28,6 +40,7 @@
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# Authors: Steve Reinhardt
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# Nathan Binkert
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# Gabe Black
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# Andreas Hansson
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#####################################################################
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#
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@@ -1324,10 +1337,11 @@ AllMemory = AddrRange(0, MaxAddr)
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# Port reference: encapsulates a reference to a particular port on a
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# particular SimObject.
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class PortRef(object):
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def __init__(self, simobj, name):
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def __init__(self, simobj, name, role):
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assert(isSimObject(simobj) or isSimObjectClass(simobj))
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self.simobj = simobj
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self.name = name
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self.role = role
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self.peer = None # not associated with another port yet
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self.ccConnected = False # C++ port connection done?
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self.index = -1 # always -1 for non-vector ports
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@@ -1397,12 +1411,24 @@ class PortRef(object):
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def ccConnect(self):
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from m5.internal.pyobject import connectPorts
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if self.role == 'SLAVE':
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# do nothing and let the master take care of it
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return
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if self.ccConnected: # already done this
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return
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peer = self.peer
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if not self.peer: # nothing to connect to
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return
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# check that we connect a master to a slave
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if self.role == peer.role:
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raise TypeError, \
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"cannot connect '%s' and '%s' due to identical role '%s'" \
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% (peer, self, self.role)
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try:
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# self is always the master and peer the slave
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connectPorts(self.simobj.getCCObject(), self.name, self.index,
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peer.simobj.getCCObject(), peer.name, peer.index)
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except:
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@@ -1416,8 +1442,8 @@ class PortRef(object):
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# A reference to an individual element of a VectorPort... much like a
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# PortRef, but has an index.
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class VectorPortElementRef(PortRef):
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def __init__(self, simobj, name, index):
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PortRef.__init__(self, simobj, name)
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def __init__(self, simobj, name, role, index):
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PortRef.__init__(self, simobj, name, role)
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self.index = index
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def __str__(self):
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@@ -1426,10 +1452,11 @@ class VectorPortElementRef(PortRef):
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# A reference to a complete vector-valued port (not just a single element).
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# Can be indexed to retrieve individual VectorPortElementRef instances.
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class VectorPortRef(object):
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def __init__(self, simobj, name):
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def __init__(self, simobj, name, role):
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assert(isSimObject(simobj) or isSimObjectClass(simobj))
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self.simobj = simobj
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self.name = name
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self.role = role
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self.elements = []
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def __str__(self):
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@@ -1444,7 +1471,7 @@ class VectorPortRef(object):
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raise TypeError, "VectorPort index must be integer"
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if key >= len(self.elements):
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# need to extend list
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ext = [VectorPortElementRef(self.simobj, self.name, i)
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ext = [VectorPortElementRef(self.simobj, self.name, self.role, i)
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for i in range(len(self.elements), key+1)]
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self.elements.extend(ext)
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return self.elements[key]
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@@ -1488,34 +1515,62 @@ class VectorPortRef(object):
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# logical port in the SimObject class, not a particular port on a
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# SimObject instance. The latter are represented by PortRef objects.
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class Port(object):
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# Port("description")
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def __init__(self, *args):
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if len(args) == 1:
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self.desc = args[0]
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else:
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raise TypeError, 'wrong number of arguments'
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# self.name is set by SimObject class on assignment
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# e.g., pio_port = Port("blah") sets self.name to 'pio_port'
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# Generate a PortRef for this port on the given SimObject with the
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# given name
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def makeRef(self, simobj):
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return PortRef(simobj, self.name)
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return PortRef(simobj, self.name, self.role)
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# Connect an instance of this port (on the given SimObject with
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# the given name) with the port described by the supplied PortRef
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def connect(self, simobj, ref):
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self.makeRef(simobj).connect(ref)
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class MasterPort(Port):
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# MasterPort("description")
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def __init__(self, *args):
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if len(args) == 1:
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self.desc = args[0]
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self.role = 'MASTER'
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else:
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raise TypeError, 'wrong number of arguments'
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class SlavePort(Port):
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# SlavePort("description")
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def __init__(self, *args):
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if len(args) == 1:
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self.desc = args[0]
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self.role = 'SLAVE'
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else:
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raise TypeError, 'wrong number of arguments'
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# VectorPort description object. Like Port, but represents a vector
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# of connections (e.g., as on a Bus).
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class VectorPort(Port):
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def __init__(self, *args):
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Port.__init__(self, *args)
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self.isVec = True
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def makeRef(self, simobj):
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return VectorPortRef(simobj, self.name)
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return VectorPortRef(simobj, self.name, self.role)
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class VectorMasterPort(VectorPort):
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# VectorMasterPort("description")
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def __init__(self, *args):
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if len(args) == 1:
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self.desc = args[0]
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self.role = 'MASTER'
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VectorPort.__init__(self, *args)
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else:
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raise TypeError, 'wrong number of arguments'
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class VectorSlavePort(VectorPort):
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# VectorSlavePort("description")
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def __init__(self, *args):
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if len(args) == 1:
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self.desc = args[0]
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self.role = 'SLAVE'
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VectorPort.__init__(self, *args)
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else:
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raise TypeError, 'wrong number of arguments'
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# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
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# proxy objects (via set_param_desc()) so that proxy error messages
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@@ -1549,6 +1604,7 @@ __all__ = ['Param', 'VectorParam',
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'MaxAddr', 'MaxTick', 'AllMemory',
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'Time',
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'NextEthernetAddr', 'NULL',
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'Port', 'VectorPort']
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'MasterPort', 'SlavePort',
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'VectorMasterPort', 'VectorSlavePort']
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import SimObject
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