diff --git a/src/arch/amdgpu/vega/insts/gpu_static_inst.cc b/src/arch/amdgpu/vega/insts/gpu_static_inst.cc index ffaffab850..35819f0d05 100644 --- a/src/arch/amdgpu/vega/insts/gpu_static_inst.cc +++ b/src/arch/amdgpu/vega/insts/gpu_static_inst.cc @@ -36,7 +36,6 @@ #include "arch/amdgpu/vega/gpu_decoder.hh" #include "arch/amdgpu/vega/insts/instructions.hh" #include "debug/GPUExec.hh" -#include "gpu-compute/flexible_pool_manager.hh" #include "gpu-compute/shader.hh" namespace gem5 diff --git a/src/arch/amdgpu/vega/insts/instructions.cc b/src/arch/amdgpu/vega/insts/instructions.cc index 96ef0318e2..999eeacce4 100644 --- a/src/arch/amdgpu/vega/insts/instructions.cc +++ b/src/arch/amdgpu/vega/insts/instructions.cc @@ -1903,11 +1903,12 @@ namespace VegaISA Inst_SOPK__S_MULK_I32::execute(GPUDynInstPtr gpuDynInst) { ScalarRegI16 simm16 = instData.SIMM16; + ConstScalarOperandI32 src(gpuDynInst, instData.SDST); ScalarOperandI32 sdst(gpuDynInst, instData.SDST); - sdst.read(); + src.read(); - sdst = sdst.rawData() * (ScalarRegI32)simm16; + sdst = src.rawData() * (ScalarRegI32)simm16; sdst.write(); } // execute @@ -4172,7 +4173,7 @@ namespace VegaISA DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n", wf->computeUnit->cu_id, wf->wgId, refCount); - wf->computeUnit->registerManager.freeRegisters(wf); + wf->computeUnit->registerManager->freeRegisters(wf); wf->computeUnit->stats.completedWfs++; wf->computeUnit->activeWaves--; @@ -5641,7 +5642,7 @@ namespace VegaISA sdata.read(); std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(), - 4 * sizeof(ScalarRegU32)); + sizeof(gpuDynInst->scalar_data)); if (instData.IMM) { offset = extData.OFFSET; diff --git a/src/arch/amdgpu/vega/operand.hh b/src/arch/amdgpu/vega/operand.hh index 1c37a0f76f..e9e1fd03fc 100644 --- a/src/arch/amdgpu/vega/operand.hh +++ b/src/arch/amdgpu/vega/operand.hh @@ -154,7 +154,7 @@ namespace VegaISA ComputeUnit *cu = _gpuDynInst->computeUnit(); for (auto i = 0; i < NumDwords; ++i) { - int vgprIdx = cu->registerManager.mapVgpr(wf, _opIdx + i); + int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx + i); vrfData[i] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx); DPRINTF(GPUVRF, "Read v[%d]\n", vgprIdx); @@ -208,7 +208,7 @@ namespace VegaISA ? _gpuDynInst->exec_mask : wf->execMask(); if (NumDwords == 1) { - int vgprIdx = cu->registerManager.mapVgpr(wf, _opIdx); + int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx); vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx); assert(vrfData[0]); auto reg_file_vgpr = vrfData[0]->template as(); @@ -224,8 +224,8 @@ namespace VegaISA DPRINTF(GPUVRF, "Write v[%d]\n", vgprIdx); cu->vrf[wf->simdId]->printReg(wf, vgprIdx); } else if (NumDwords == 2) { - int vgprIdx0 = cu->registerManager.mapVgpr(wf, _opIdx); - int vgprIdx1 = cu->registerManager.mapVgpr(wf, _opIdx + 1); + int vgprIdx0 = cu->registerManager->mapVgpr(wf, _opIdx); + int vgprIdx1 = cu->registerManager->mapVgpr(wf, _opIdx + 1); vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx0); vrfData[1] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx1); assert(vrfData[0]); @@ -521,7 +521,7 @@ namespace VegaISA ScalarRegU64 exec_mask = _gpuDynInst->wavefront()-> execMask().to_ullong(); std::memcpy((void*)srfData.data(), (void*)&exec_mask, - sizeof(srfData)); + sizeof(exec_mask)); DPRINTF(GPUSRF, "Read EXEC\n"); DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask); } @@ -538,7 +538,7 @@ namespace VegaISA ScalarRegU32 exec_mask_hi = bits(exec_mask, 63, 32); std::memcpy((void*)srfData.data(), (void*)&exec_mask_hi, - sizeof(srfData)); + sizeof(exec_mask_hi)); DPRINTF(GPUSRF, "Read EXEC_HI\n"); DPRINTF(GPUSRF, "EXEC_HI = %#x\n", exec_mask_hi); } @@ -553,7 +553,7 @@ namespace VegaISA { typename OpTraits::FloatT pos_half = 0.5; std::memcpy((void*)srfData.data(), (void*)&pos_half, - sizeof(srfData)); + sizeof(pos_half)); } break; @@ -561,44 +561,44 @@ namespace VegaISA { typename OpTraits::FloatT neg_half = -0.5; std::memcpy((void*)srfData.data(), (void*)&neg_half, - sizeof(srfData)); + sizeof(neg_half)); } break; case REG_POS_ONE: { typename OpTraits::FloatT pos_one = 1.0; - std::memcpy(srfData.data(), &pos_one, sizeof(srfData)); + std::memcpy(srfData.data(), &pos_one, sizeof(pos_one)); } break; case REG_NEG_ONE: { typename OpTraits::FloatT neg_one = -1.0; - std::memcpy(srfData.data(), &neg_one, sizeof(srfData)); + std::memcpy(srfData.data(), &neg_one, sizeof(neg_one)); } break; case REG_POS_TWO: { typename OpTraits::FloatT pos_two = 2.0; - std::memcpy(srfData.data(), &pos_two, sizeof(srfData)); + std::memcpy(srfData.data(), &pos_two, sizeof(pos_two)); } break; case REG_NEG_TWO: { typename OpTraits::FloatT neg_two = -2.0; - std::memcpy(srfData.data(), &neg_two, sizeof(srfData)); + std::memcpy(srfData.data(), &neg_two, sizeof(neg_two)); } break; case REG_POS_FOUR: { typename OpTraits::FloatT pos_four = 4.0; - std::memcpy(srfData.data(), &pos_four, sizeof(srfData)); + std::memcpy(srfData.data(), &pos_four, sizeof(pos_four)); } break; case REG_NEG_FOUR: { typename OpTraits::FloatT neg_four = -4.0; std::memcpy((void*)srfData.data(), (void*)&neg_four , - sizeof(srfData)); + sizeof(neg_four)); } break; case REG_PI: @@ -611,10 +611,10 @@ namespace VegaISA if (sizeof(DataType) == sizeof(ScalarRegF64)) { std::memcpy((void*)srfData.data(), - (void*)&pi_u64, sizeof(srfData)); + (void*)&pi_u64, sizeof(pi_u64)); } else { std::memcpy((void*)srfData.data(), - (void*)&pi_u32, sizeof(srfData)); + (void*)&pi_u32, sizeof(pi_u32)); } } break; @@ -648,16 +648,16 @@ namespace VegaISA if (_opIdx == REG_VCC_LO) { sgprIdx = cu->registerManager - .mapSgpr(wf, wf->reservedScalarRegs - 2 + dword); + ->mapSgpr(wf, wf->reservedScalarRegs - 2 + dword); } else if (_opIdx == REG_FLAT_SCRATCH_HI) { sgprIdx = cu->registerManager - .mapSgpr(wf, wf->reservedScalarRegs - 3 + dword); + ->mapSgpr(wf, wf->reservedScalarRegs - 3 + dword); } else if (_opIdx == REG_FLAT_SCRATCH_LO) { assert(NumDwords == 1); sgprIdx = cu->registerManager - .mapSgpr(wf, wf->reservedScalarRegs - 4 + dword); + ->mapSgpr(wf, wf->reservedScalarRegs - 4 + dword); } else { - sgprIdx = cu->registerManager.mapSgpr(wf, _opIdx + dword); + sgprIdx = cu->registerManager->mapSgpr(wf, _opIdx + dword); } assert(sgprIdx > -1);