From 5a6901c405378b01e6dff19b5d5820609612976a Mon Sep 17 00:00:00 2001
From: Yu-Cheng Chang <rogerycchang@google.com>
Date: Wed, 13 Dec 2023 00:23:28 +0800
Subject: [PATCH] configs: Make riscv/fs_linux work in build/ALL/gem5.opt
 (#655)

Change-Id: If9add7dc5e9c5600f769d27817da41466158942b
---
 configs/common/Options.py         | 26 ++++++++++++++++----------
 configs/example/riscv/fs_linux.py | 20 +++++++-------------
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/configs/common/Options.py b/configs/common/Options.py
index c15410d41a..97335f13b9 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -37,6 +37,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import argparse
+from typing import Optional
 
 from common import (
     CpuConfig,
@@ -48,6 +49,7 @@ import m5
 from m5.defines import buildEnv
 from m5.objects import *
 
+from gem5.isas import ISA
 from gem5.runtime import get_supported_isas
 
 vio_9p_help = """\
@@ -242,10 +244,13 @@ def addNoISAOptions(parser):
 # Add common options that assume a non-NULL ISA.
 
 
-def addCommonOptions(parser):
+def addCommonOptions(parser, default_isa: Optional[ISA] = None):
     # start by adding the base options that do not assume an ISA
     addNoISAOptions(parser)
-    isa = list(get_supported_isas())[0]
+    if default_isa is None:
+        isa = list(get_supported_isas())[0]
+    else:
+        isa = default_isa
 
     # system options
     parser.add_argument(
@@ -790,12 +795,20 @@ def addFSOptions(parser):
         "files in the gem5 output directory",
     )
 
-    if buildEnv["USE_ARM_ISA"]:
+    if buildEnv["USE_ARM_ISA"] or buildEnv["USE_RISCV_ISA"]:
         parser.add_argument(
             "--bare-metal",
             action="store_true",
             help="Provide the raw system without the linux specific bits",
         )
+        parser.add_argument(
+            "--dtb-filename",
+            action="store",
+            type=str,
+            help="Specifies device tree blob file to use with device-tree-"
+            "enabled kernels",
+        )
+    if buildEnv["USE_ARM_ISA"]:
         parser.add_argument(
             "--list-machine-types",
             action=ListPlatform,
@@ -808,13 +821,6 @@ def addFSOptions(parser):
             choices=ObjectList.platform_list.get_names(),
             default="VExpress_GEM5_V1",
         )
-        parser.add_argument(
-            "--dtb-filename",
-            action="store",
-            type=str,
-            help="Specifies device tree blob file to use with device-tree-"
-            "enabled kernels",
-        )
         parser.add_argument(
             "--enable-context-switch-stats-dump",
             action="store_true",
diff --git a/configs/example/riscv/fs_linux.py b/configs/example/riscv/fs_linux.py
index 075b4a0069..c0643c883d 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -52,6 +52,8 @@ from m5.util import (
 )
 from m5.util.fdthelper import *
 
+from gem5.utils.requires import requires
+
 addToPath("../../")
 
 from common import (
@@ -68,6 +70,9 @@ from common.FSConfig import *
 from common.SysPaths import *
 from ruby import Ruby
 
+# Run a check to ensure the RISC-V ISA is complied into gem5.
+requires(isa_required=ISA.RISCV)
+
 # ------------------------- Usage Instructions ------------------------- #
 # Common system confirguration options (cpu types, num cpus, checkpointing
 # etc.) should be supported
@@ -135,20 +140,8 @@ def generateDtb(system):
 
 # ----------------------------- Add Options ---------------------------- #
 parser = argparse.ArgumentParser()
-Options.addCommonOptions(parser)
+Options.addCommonOptions(parser, ISA.RISCV)
 Options.addFSOptions(parser)
-parser.add_argument(
-    "--bare-metal",
-    action="store_true",
-    help="Provide the raw system without the linux specific bits",
-)
-parser.add_argument(
-    "--dtb-filename",
-    action="store",
-    type=str,
-    help="Specifies device tree blob file to use with device-tree-"
-    "enabled kernels",
-)
 parser.add_argument(
     "--virtio-rng", action="store_true", help="Enable VirtIORng device"
 )
@@ -158,6 +151,7 @@ args = parser.parse_args()
 
 # CPU and Memory
 (CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(args)
+assert issubclass(CPUClass, RiscvCPU)
 MemClass = Simulation.setMemClass(args)
 
 np = args.num_cpus