derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fix mostly floating point related

Browse Source 
src/arch/sparc/floatregfile.cc:
    fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
    fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
    add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
    include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
    print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
    fix printing of float registers

--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
This commit is contained in:
Ali Saidi
2007-02-02 18:04:42 -05:00
parent 5c7192daed
commit 592f35ac0f
6 changed files with 118 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/cpu/exetrace.cc
View File

@@ -450,16 +450,13 @@ Trace::InstRecord::dump(ostream &outs)
diffTlb = true;
}
if ((diffPC || diffCC || diffInst || diffIntRegs ||
if (diffPC || diffCC || diffInst || diffIntRegs ||
diffFpRegs || diffTpc || diffTnpc || diffTstate ||
diffTt || diffHpstate || diffHtstate || diffHtba ||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
diffGl || diffAsi || diffPil || diffCwp || diffCansave ||
diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
&& !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
&& shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
) {
{
outs << "Differences found between M5 and Legion:";
if (diffPC)
@@ -639,7 +636,7 @@ Trace::InstRecord::dump(ostream &outs)
char label[8];
sprintf(label, "%%f%d", x);
printRegPair(outs, label,
thread->readFloatRegBits(x,FloatRegFile::DoubleWidth),
thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth),
shared_data->fpregs[x]);
}
}