derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

configs, mem: MemInterface generating its own controller

Browse Source 
We are adding a controller method to MemInterface objects making
them able to generate the appropriate memory controller.

This will bring the following benefits

a) Semplification: It will simplify MemConfig.config_mem
b) Reusability: Scripts not using config_mem
won't have to duplicate the if...else checks
c) Modularity: Users will be able to define their own
dram interfaces without needing to handle the mem_ctrl
mapping in the shared MemConfig.py module

Change-Id: I4b836fd7c91675cf7aacc644f25989484d5be3ec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42074
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-03-02 09:38:20 +00:00
parent 1c35c00c4f
commit 588df4be85
4 changed files with 39 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
configs/common/MemConfig.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2013, 2017, 2020 ARM Limited
# Copyright (c) 2013, 2017, 2020-2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -218,24 +218,7 @@ def config_mem(options, system):
"latency to 1ns.")
# Create the controller that will drive the interface
if opt_mem_type == "HMC_2500_1x32":
# The static latency of the vault controllers is estimated
# to be smaller than a full DRAM channel controller
mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch = 8,
static_backend_latency = '4ns',
static_frontend_latency = '4ns')
elif opt_mem_type == "SimpleMemory":
mem_ctrl = m5.objects.SimpleMemory()
elif opt_mem_type == "QoSMemSinkInterface":
mem_ctrl = m5.objects.QoSMemSinkCtrl()
else:
mem_ctrl = m5.objects.MemCtrl()
# Hookup the controller to the interface and add to the list
if opt_mem_type == "QoSMemSinkInterface":
mem_ctrl.interface = dram_intf
elif opt_mem_type != "SimpleMemory":
mem_ctrl.dram = dram_intf
mem_ctrl = dram_intf.controller()
mem_ctrls.append(mem_ctrl)