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configs,stdlib,tests: Remove get_runtime_isa() (#241)

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`get_runtime_isa()` has been deprecated for some time. It is a leftover
piece of code from when gem5 was compiled to a single ISA and that ISA
used to configure the simulated system to use that ISA. Since multi-ISA
compilations are possible, `get_runtime_isa()` should not be used.
Unless the gem5 binary is compiled to a single ISA, a failure will
occur.

The new proceedure for specify which ISA to use is by the setting of the
correct `BaseCPU` implementation. E.g., `X86SimpleTimingCPU` of
`ArmO3CPU`.

This patch removes the remaining `get_runtime_isa()` instances and
removes the function itself. The `SimpleCore` class has been updated to
allow for it's CPU factory to return a class, needed by scripts in
"configs/common".

The deprecated functionality in the standard library, which allowed for
the specifying of an ISA when setting up a processor and/or core has
also been removed. Setting an ISA is now manditory.

Fixes #216.
This commit is contained in:
Bobby R. Bruce
2023-12-04 09:53:35 -08:00
committed by GitHub
parent 7b98641953
commit 569e21f798
20 changed files with 125 additions and 178 deletions
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15
src/python/gem5/components/processors/base_cpu_core.py
View File

@@ -40,7 +40,6 @@ from m5.objects import (
from m5.params import PcCountPair
from ...isas import ISA
from ...runtime import get_runtime_isa
from ...utils.override import overrides
from ...utils.requires import requires
from .abstract_core import AbstractCore
@@ -51,17 +50,19 @@ class BaseCPUCore(AbstractCore):
An stdlib AbstractCore subclass which wraps a BaseCPU SimObject type.
"""
def __init__(self, core: BaseCPU, isa: Optional[ISA] = None):
def __init__(self, core: BaseCPU, isa: ISA):
super().__init__()
# There is some annoying redundancy here. The BaseCPU type already
# defines the ISA, so here we are defining it twice. However, there
# currently isn't a good way to get the ISA from the BaseCPU Type.
if isa:
requires(isa_required=isa)
self._isa = isa
else:
self._isa = get_runtime_isa()
#
# TODO: Have some helper function to get the ISA from a BaseCPU type.
# This may just be a cause of using `instanceof`:
# e.g., `if instanceof(cpu, X86Cpu): return ISA.X86`.
#
requires(isa_required=isa)
self._isa = isa
self.core = core
self.core.createThreads()

39
src/python/gem5/components/processors/simple_core.py
View File

@@ -29,7 +29,6 @@ import platform
from typing import Optional
from ...isas import ISA
from ...runtime import get_runtime_isa
from ...utils.requires import requires
from .base_cpu_core import BaseCPUCore
from .cpu_types import CPUTypes
@@ -41,17 +40,8 @@ class SimpleCore(BaseCPUCore):
`SimpleCore` creates a single `SimObject` of that type.
"""
def __init__(
self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None
):
# If the ISA is not specified, we infer it via the `get_runtime_isa`
# function.
if isa:
requires(isa_required=isa)
isa = isa
else:
isa = get_runtime_isa()
def __init__(self, cpu_type: CPUTypes, core_id: int, isa: ISA):
requires(isa_required=isa)
super().__init__(
core=SimpleCore.cpu_simobject_factory(
isa=isa, cpu_type=cpu_type, core_id=core_id
@@ -65,15 +55,14 @@ class SimpleCore(BaseCPUCore):
return self._cpu_type
@classmethod
def cpu_simobject_factory(cls, cpu_type: CPUTypes, isa: ISA, core_id: int):
def cpu_class_factory(cls, cpu_type: CPUTypes, isa: ISA) -> type:
"""
A factory used to return the SimObject core object given the cpu type,
A factory used to return the SimObject type given the cpu type,
and ISA target. An exception will be thrown if there is an
incompatibility.
:param cpu_type: The target CPU type.
:param isa: The target ISA.
:param core_id: The id of the core to be returned.
"""
assert isa is not None
@@ -145,4 +134,22 @@ class SimpleCore(BaseCPUCore):
"gem5."
)
return to_return_cls(cpu_id=core_id)
return to_return_cls
@classmethod
def cpu_simobject_factory(
cls, cpu_type: CPUTypes, isa: ISA, core_id: int
) -> BaseCPUCore:
"""
A factory used to return the SimObject core object given the cpu type,
and ISA target. An exception will be thrown if there is an
incompatibility.
:param cpu_type: The target CPU type.
:param isa: The target ISA.
:param core_id: The id of the core to be returned.
"""
return cls.cpu_class_factory(cpu_type=cpu_type, isa=isa)(
cpu_id=core_id
)

18
src/python/gem5/components/processors/simple_processor.py
View File

@@ -41,28 +41,14 @@ class SimpleProcessor(BaseCPUProcessor):
same CPUType.
"""
def __init__(
self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] = None
) -> None:
def __init__(self, cpu_type: CPUTypes, num_cores: int, isa: ISA) -> None:
"""
:param cpu_type: The CPU type for each type in the processor.
:param num_cores: The number of CPU cores in the processor.
:param isa: The ISA of the processor. This argument is optional. If not
set the ``runtime.get_runtime_isa`` is used to determine the
ISA at runtime. **WARNING**: This functionality is deprecated.
It is recommended you explicitly set your ISA via SimpleProcessor
construction.
:param isa: The ISA of the processor.
"""
if not isa:
warn(
"An ISA for the SimpleProcessor was not set. This will "
"result in usage of `runtime.get_runtime_isa` to obtain the "
"ISA. This function is deprecated and will be removed in "
"future releases of gem5. Please explicitly state the ISA "
"via the processor constructor."
)
super().__init__(
cores=[
SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa)

21
src/python/gem5/components/processors/simple_switchable_processor.py
View File

@@ -53,31 +53,18 @@ class SimpleSwitchableProcessor(SwitchableProcessor):
starting_core_type: CPUTypes,
switch_core_type: CPUTypes,
num_cores: int,
isa: Optional[ISA] = None,
isa: ISA = None,
) -> None:
"""
:param starting_core_type: The CPU type for each type in the processor
to start with (i.e., when the simulation has
just started).
:param switch_core_types: The CPU type for each core, to be switched
to.
:param switch_core_types: The CPU type for each core, to be switched to.
:param isa: The ISA of the processor. This argument is optional. If not
set the ``runtime.get_runtime_isa`` is used to determine the
ISA at runtime. **WARNING**: This functionality is deprecated.
It is recommended you explicitly set your ISA via
SimpleSwitchableProcessor construction.
:param isa: The ISA of the processor.
"""
if not isa:
warn(
"An ISA for the SimpleSwitchableProcessor was not set. This "
"will result in usage of `runtime.get_runtime_isa` to obtain "
"the ISA. This function is deprecated and will be removed in "
"future releases of gem5. Please explicitly state the ISA "
"via the processor constructor."
)
if num_cores <= 0:
raise AssertionError("Number of cores must be a positive integer!")

37
src/python/gem5/runtime.py
View File

@@ -60,43 +60,6 @@ def get_supported_isas() -> Set[ISA]:
return supported_isas
def get_runtime_isa() -> ISA:
"""
Returns a single target ISA at runtime.
This determined via the "TARGET_ISA" parameter, which is set at
compilation. If not set, but only one ISA is compiled, we assume it's the
one ISA. If neither the "TARGET_ISA" parameter is set and there are
multiple ISA targets, an exception is thrown.
.. warning::
This function is deprecated and may be removed in future versions of
gem5. This function should not be relied upon to run gem5 simulations.
:returns: The target ISA.
"""
warn(
"The `get_runtime_isa` function is deprecated. Please migrate away "
"from using this function."
)
if "TARGET_ISA" in buildEnv.keys():
return get_isa_from_str(buildEnv["TARGET_ISA"])
supported_isas = get_supported_isas()
if len(supported_isas) == 1:
return next(iter(supported_isas))
raise Exception(
"Cannot determine the the runtime ISA. Either the "
"'TARGET_ISA' parameter must be set or the binary only "
"compiled to one ISA."
)
def get_runtime_coherence_protocol() -> CoherenceProtocol:
"""Gets the cache coherence protocol.