MEM: Removing the default port peer from Python ports

In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.

src/python/m5/SimObject.py

@@ -273,8 +273,6 @@ class MetaSimObject(type):
         assert(not hasattr(port, 'name'))
         port.name = name
         cls._ports[name] = port
-        if hasattr(port, 'default'):
-            cls._cls_get_port_ref(name).connect(port.default)
 
     # same as _get_port_ref, effectively, but for classes
     def _cls_get_port_ref(cls, attr):

src/python/m5/params.py

@@ -1488,13 +1488,10 @@ class VectorPortRef(object):
 # logical port in the SimObject class, not a particular port on a
 # SimObject instance.  The latter are represented by PortRef objects.
 class Port(object):
-    # Port("description") or Port(default, "description")
+    # Port("description")
     def __init__(self, *args):
         if len(args) == 1:
             self.desc = args[0]
-        elif len(args) == 2:
-            self.default = args[0]
-            self.desc = args[1]
         else:
             raise TypeError, 'wrong number of arguments'
         # self.name is set by SimObject class on assignment