From 540c3fc7ef323b4e67f0943881b5d1a2c457c010 Mon Sep 17 00:00:00 2001
From: Yang Liu <numbksco@gmail.com>
Date: Tue, 10 Jan 2023 14:29:52 +0800
Subject: [PATCH] arch: Add vector function unit and OpClass enums

These enums are needed for risc-v vector extension

Change-Id: Ia61682c43c89ac2043fb9d1d5c349dfd646fb88d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67293
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Roger Chang <rogerycchang@google.com>
---
 src/cpu/FuncUnit.py | 19 +++++++++++++++++++
 src/cpu/op_class.hh | 24 ++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 4a2733afc0..a1050de242 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -98,6 +98,25 @@ class OpClass(Enum):
         "FloatMemWrite",
         "IprAccess",
         "InstPrefetch",
+        "VectorUnitStrideLoad",
+        "VectorUnitStrideStore",
+        "VectorUnitStrideMaskLoad",
+        "VectorUnitStrideMaskStore",
+        "VectorStridedLoad",
+        "VectorStridedStore",
+        "VectorIndexedLoad",
+        "VectorIndexedStore",
+        "VectorUnitStrideFaultOnlyFirstLoad",
+        "VectorWholeRegisterLoad",
+        "VectorWholeRegisterStore",
+        "VectorIntegerArith",
+        "VectorFloatArith",
+        "VectorFloatConvert",
+        "VectorIntegerReduce",
+        "VectorFloatReduce",
+        "VectorMisc",
+        "VectorIntegerExtension",
+        "VectorConfig",
     ]
 
 
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 4de018f21b..94d2794c76 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -108,6 +108,30 @@ static const OpClass FloatMemReadOp = enums::FloatMemRead;
 static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
 static const OpClass IprAccessOp = enums::IprAccess;
 static const OpClass InstPrefetchOp = enums::InstPrefetch;
+static const OpClass VectorUnitStrideLoadOp = enums::VectorUnitStrideLoad;
+static const OpClass VectorUnitStrideStoreOp = enums::VectorUnitStrideStore;
+static const OpClass VectorUnitStrideMaskLoadOp
+             = enums::VectorUnitStrideMaskLoad;
+static const OpClass VectorUnitStrideMaskStoreOp
+             = enums::VectorUnitStrideMaskStore;
+static const OpClass VectorStridedLoadOp = enums::VectorStridedLoad;
+static const OpClass VectorStridedStoreOp = enums::VectorStridedStore;
+static const OpClass VectorIndexedLoadOp = enums::VectorIndexedLoad;
+static const OpClass VectorIndexedStoreOp = enums::VectorIndexedStore;
+static const OpClass VectorUnitStrideFaultOnlyFirstLoadOp
+             = enums::VectorUnitStrideFaultOnlyFirstLoad;
+static const OpClass VectorWholeRegisterLoadOp
+             = enums::VectorWholeRegisterLoad;
+static const OpClass VectorWholeRegisterStoreOp
+             = enums::VectorWholeRegisterStore;
+static const OpClass VectorIntegerArithOp = enums::VectorIntegerArith;
+static const OpClass VectorFloatArithOp = enums::VectorFloatArith;
+static const OpClass VectorFloatConvertOp = enums::VectorFloatConvert;
+static const OpClass VectorIntegerReduceOp = enums::VectorIntegerReduce;
+static const OpClass VectorFloatReduceOp = enums::VectorFloatReduce;
+static const OpClass VectorMiscOp = enums::VectorMisc;
+static const OpClass VectorIntegerExtensionOp = enums::VectorIntegerExtension;
+static const OpClass VectorConfigOp = enums::VectorConfig;
 static const OpClass Num_OpClasses = enums::Num_OpClass;
 
 } // namespace gem5