cpu: Restructure RAS

The return address stack (RAS) is restructured to be a separate SimObject.
This enables disabling the RAS and better separation of the functionality.
Furthermore, easier statistics and debugging.

Change-Id: I8aacf7d4c8e308165d0e7e15bc5a5d0df77f8192
Signed-off-by: David Schall <david.schall@ed.ac.uk>

src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

@@ -96,7 +96,7 @@ class U74FUPool(MinorFUPool):
 
 class U74BP(TournamentBP):
     btb = SimpleBTB(numEntries=32)
-    RASSize = 12
+    ras = ReturnAddrStack(numEntries=12)
     localHistoryTableSize = 4096  # is 3.6 KiB but gem5 requires power of 2
     localPredictorSize = 16384
     globalPredictorSize = 16384