diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a3e0ce6c2b..b3d6726d92 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -437,6 +437,16 @@ ISA::startup(ThreadContext *tc)
     afterStartup = true;
 }
 
+void
+ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
+{
+    pmu->setThreadContext(new_tc);
+
+    if (system && gicv3CpuInterface) {
+        gicv3CpuInterface->setISA(this);
+        gicv3CpuInterface->setThreadContext(new_tc);
+    }
+}
 
 RegVal
 ISA::readMiscRegNoEffect(int misc_reg) const
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8f2e0d26b4..5fec2dbb94 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -743,6 +743,9 @@ namespace ArmISA
 
         void startup(ThreadContext *tc);
 
+        void takeOverFrom(ThreadContext *new_tc,
+                          ThreadContext *old_tc) override;
+
         Enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
 
         /** Returns true if the ISA has a GICv3 cpu interface */