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mem: Reverse order of write/read mem queue check

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For atomic RMW instructions that go directly to memory, we want to put
them on the write queue instead of the read queue. Swap the if/else
condition to accomplish this.

Note: This is ignoring the read latency of the RMW, but these
instructions should usually be handled in caches anyway.

Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Jason Lowe-Power
2019-04-04 14:10:16 -07:00
parent 07eca72e1a
commit 529d0cdbfe
1 changed files with 15 additions and 15 deletions
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30
src/mem/dram_ctrl.cc
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@@ -644,21 +644,7 @@ DRAMCtrl::recvTimingReq(PacketPtr pkt)
qosSchedule( { &readQueue, &writeQueue }, burstSize, pkt);
// check local buffers and do not accept if full
if (pkt->isRead()) {
assert(size != 0);
if (readQueueFull(dram_pkt_count)) {
DPRINTF(DRAM, "Read queue full, not accepting\n");
// remember that we have to retry this port
retryRdReq = true;
numRdRetry++;
return false;
} else {
addToReadQueue(pkt, dram_pkt_count);
readReqs++;
bytesReadSys += size;
}
} else {
assert(pkt->isWrite());
if (pkt->isWrite()) {
assert(size != 0);
if (writeQueueFull(dram_pkt_count)) {
DPRINTF(DRAM, "Write queue full, not accepting\n");
@@ -671,6 +657,20 @@ DRAMCtrl::recvTimingReq(PacketPtr pkt)
writeReqs++;
bytesWrittenSys += size;
}
} else {
assert(pkt->isRead());
assert(size != 0);
if (readQueueFull(dram_pkt_count)) {
DPRINTF(DRAM, "Read queue full, not accepting\n");
// remember that we have to retry this port
retryRdReq = true;
numRdRetry++;
return false;
} else {
addToReadQueue(pkt, dram_pkt_count);
readReqs++;
bytesReadSys += size;
}
}
return true;