diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 665b2989c8..9cd068f7fa 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -749,15 +749,16 @@ UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) // If the mnemonic isn't defined this has to be an unknown instruction. assert(unknown || mnemonic != NULL); + auto arm_inst = static_cast(inst.get()); if (disabled) { panic("Attempted to execute disabled instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); + "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); } else if (unknown) { panic("Attempted to execute unknown instruction (inst 0x%08x)", - machInst); + arm_inst->encoding()); } else { panic("Attempted to execute unimplemented instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); + "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); } } diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 3f29865252..8efb81a6cf 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -324,7 +324,7 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32)); + return csprintf("%-10s (inst %#08x)", "unknown", encoding()); } McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 7df2f76ed5..c219bd9ad5 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -78,7 +78,7 @@ RegRegRegImmOp64::generateDisassembly( std::string UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32)); + return csprintf("%-10s (inst %#08x)", "unknown", encoding()); } Fault