misc: Merge branch v21.0.0.0 into develop

This incorporates the last of the v21.0 staging branch changes into the
develop branch.

Change-Id: I89349ac5c52fd454eb87d6199ea5ccde0d50dda3

src/dev/riscv/Clint.py

@@ -37,6 +37,7 @@ from m5.objects.Device import BasicPioDevice
 from m5.objects.IntPin import IntSinkPin
 from m5.params import *
 from m5.proxy import *
+from m5.util.fdthelper import *
 
 class Clint(BasicPioDevice):
     """
@@ -51,3 +52,21 @@ class Clint(BasicPioDevice):
     intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
     int_pin = IntSinkPin('Pin to receive RTC signal')
     pio_size = Param.Addr(0xC000, "PIO Size")
+
+    def generateDeviceTree(self, state):
+        node = self.generateBasicPioDeviceNode(state, "clint", self.pio_addr,
+                                               self.pio_size)
+
+        cpus = self.system.unproxy(self).cpu
+        int_extended = list()
+        for cpu in cpus:
+            phandle = state.phandle(cpu)
+            int_extended.append(phandle)
+            int_extended.append(0x3)
+            int_extended.append(phandle)
+            int_extended.append(0x7)
+
+        node.append(FdtPropertyWords("interrupts-extended", int_extended))
+        node.appendCompatible(["riscv,clint0"])
+
+        yield node

src/dev/riscv/HiFive.py

@@ -42,6 +42,7 @@ from m5.objects.Uart import Uart8250
 from m5.objects.Terminal import Terminal
 from m5.params import *
 from m5.proxy import *
+from m5.util.fdthelper import *
 
 class HiFive(Platform):
     """HiFive Platform
@@ -111,6 +112,9 @@ class HiFive(Platform):
     uart_int_id = Param.Int(0xa, "PLIC Uart interrupt ID")
     terminal = Terminal()
 
+    # Dummy param for generating devicetree
+    cpu_count = Param.Int(0, "dummy")
+
     def _on_chip_devices(self):
         """Returns a list of on-chip peripherals
         """
@@ -167,3 +171,39 @@ class HiFive(Platform):
         """
         for device in self._off_chip_devices():
             device.pio = bus.mem_side_ports
+
+    def generateDeviceTree(self, state):
+        cpus_node = FdtNode("cpus")
+        cpus_node.append(FdtPropertyWords("timebase-frequency", [10000000]))
+        yield cpus_node
+
+        node = FdtNode("soc")
+        local_state = FdtState(addr_cells=2, size_cells=2)
+        node.append(local_state.addrCellsProperty())
+        node.append(local_state.sizeCellsProperty())
+        node.append(FdtProperty("ranges"))
+        node.appendCompatible(["simple-bus"])
+
+        for subnode in self.recurseDeviceTree(local_state):
+            node.append(subnode)
+
+        yield node
+
+    def annotateCpuDeviceNode(self, cpu, state):
+        cpu.append(FdtPropertyStrings('mmu-type', 'riscv,sv48'))
+        cpu.append(FdtPropertyStrings('status', 'okay'))
+        cpu.append(FdtPropertyStrings('riscv,isa', 'rv64imafdcsu'))
+        cpu.appendCompatible(["riscv"])
+
+        int_node = FdtNode("interrupt-controller")
+        int_state = FdtState(interrupt_cells=1)
+        int_node.append(int_state.interruptCellsProperty())
+        int_node.append(FdtProperty("interrupt-controller"))
+        int_node.appendCompatible("riscv,cpu-intc")
+
+        cpus = self.system.unproxy(self).cpu
+        phandle = int_state.phandle(cpus[self.cpu_count])
+        self.cpu_count += 1
+        int_node.append(FdtPropertyWords("phandle", [phandle]))
+
+        cpu.append(int_node)

src/dev/riscv/Plic.py

@@ -36,6 +36,7 @@
 from m5.objects.Device import BasicPioDevice
 from m5.params import *
 from m5.proxy import *
+from m5.util.fdthelper import *
 
 class Plic(BasicPioDevice):
     """
@@ -50,3 +51,30 @@ class Plic(BasicPioDevice):
     intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
     pio_size = Param.Addr(0x4000000, "PIO Size")
     n_src = Param.Int("Number of interrupt sources")
+
+    def generateDeviceTree(self, state):
+        node = self.generateBasicPioDeviceNode(state, "plic", self.pio_addr,
+                                               self.pio_size)
+
+        int_state = FdtState(addr_cells=0, interrupt_cells=1)
+        node.append(int_state.addrCellsProperty())
+        node.append(int_state.interruptCellsProperty())
+
+        phandle = int_state.phandle(self)
+        node.append(FdtPropertyWords("phandle", [phandle]))
+        node.append(FdtPropertyWords("riscv,ndev", [self.n_src - 1]))
+
+        cpus = self.system.unproxy(self).cpu
+        int_extended = list()
+        for cpu in cpus:
+            phandle = int_state.phandle(cpu)
+            int_extended.append(phandle)
+            int_extended.append(0xb)
+            int_extended.append(phandle)
+            int_extended.append(0x9)
+
+        node.append(FdtPropertyWords("interrupts-extended", int_extended))
+        node.append(FdtProperty("interrupt-controller"))
+        node.appendCompatible(["riscv,plic0"])
+
+        yield node

src/dev/riscv/PlicDevice.py

@@ -36,6 +36,7 @@
 from m5.objects.Device import BasicPioDevice
 from m5.params import *
 from m5.proxy import *
+from m5.util.fdthelper import *
 
 class PlicIntDevice(BasicPioDevice):
     type = 'PlicIntDevice'
@@ -44,3 +45,13 @@ class PlicIntDevice(BasicPioDevice):
     platform = Param.Platform(Parent.any, "Platform")
     pio_size = Param.Addr("PIO Size")
     interrupt_id = Param.Int("PLIC Interrupt ID")
+
+    def generatePlicDeviceNode(self, state, name):
+        node = self.generateBasicPioDeviceNode(state, name,
+                self.pio_addr, self.pio_size)
+
+        plic = self.platform.unproxy(self).plic
+
+        node.append(FdtPropertyWords("interrupts", [self.interrupt_id]))
+        node.append(FdtPropertyWords("interrupt-parent", state.phandle(plic)))
+        return node

src/dev/riscv/VirtIOMMIO.py

@@ -37,6 +37,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from m5.util.fdthelper import *
 
 from m5.objects.PlicDevice import PlicIntDevice
 from m5.objects.VirtIO import VirtIODummyDevice
@@ -45,3 +46,9 @@ class MmioVirtIO(PlicIntDevice):
     type = 'MmioVirtIO'
     cxx_header = 'dev/riscv/vio_mmio.hh'
     vio = Param.VirtIODeviceBase(VirtIODummyDevice(), "VirtIO device")
+
+    def generateDeviceTree(self, state):
+        node = self.generatePlicDeviceNode(state, "virtio_mmio")
+        node.appendCompatible(["virtio,mmio"])
+
+        yield node

src/dev/riscv/clint.cc

@@ -64,7 +64,9 @@ Clint::raiseInterruptPin(int id)
     for (int context_id = 0; context_id < nThread; context_id++) {
 
         // Update misc reg file
-        system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME, mtime);
+        ISA* isa = dynamic_cast<ISA*>(
+            system->threads[context_id]->getIsaPtr());
+        isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
 
         // Post timer interrupt
         uint64_t mtimecmp = registers.mtimecmp[context_id].get();

src/dev/serial/Uart.py

@@ -38,6 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
+from m5.util.fdthelper import *
+from m5.defines import buildEnv
 
 from m5.objects.Device import BasicPioDevice
 from m5.objects.Serial import SerialDevice
@@ -61,3 +63,18 @@ class Uart8250(Uart):
     type = 'Uart8250'
     cxx_header = "dev/serial/uart8250.hh"
     pio_size = Param.Addr(0x8, "Size of address range")
+
+    def generateDeviceTree(self, state):
+        if buildEnv['TARGET_ISA'] == "riscv":
+            node = self.generateBasicPioDeviceNode(
+                state, "uart", self.pio_addr, self.pio_size)
+            platform = self.platform.unproxy(self)
+            plic = platform.plic
+            node.append(
+                FdtPropertyWords("interrupts", [platform.uart_int_id]))
+            node.append(
+                FdtPropertyWords("clock-frequency", [0x384000]))
+            node.append(
+                FdtPropertyWords("interrupt-parent", state.phandle(plic)))
+            node.appendCompatible(["ns8250"])
+            yield node