From 4f72f6172ac6e44b770a590a5cfbab063ce36412 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sun, 15 Oct 2023 19:36:20 -0700 Subject: [PATCH] stdlib: Use the ISA string generator in the RiscvBoard Current hardcoded value does not support vector instructions. The new ISA string generator function allows the flexibility of using or not using the vector extension. Change-Id: Ic78c4b6629ad3813fc172f700d77ea956552e613 Signed-off-by: Hoa Nguyen --- src/python/gem5/components/boards/riscv_board.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index 450fcb7866..9b0d6454e1 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -280,7 +280,11 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): node.append(FdtPropertyWords("reg", state.CPUAddrCells(i))) node.append(FdtPropertyStrings("mmu-type", "riscv,sv48")) node.append(FdtPropertyStrings("status", "okay")) - node.append(FdtPropertyStrings("riscv,isa", "rv64imafdc")) + node.append( + FdtPropertyStrings( + "riscv,isa", core.core.isa[0].get_isa_string() + ) + ) # TODO: Should probably get this from the core. freq = self.clk_domain.clock[0].frequency node.append(FdtPropertyWords("clock-frequency", freq))