Merge m5read@m5.eecs.umich.edu:/bk/m5

into zamp.eecs.umich.edu:/.automount/fox/y/mserrano/m5_new/m5

--HG--
extra : convert_revision : bb3e977e79599c459fb32f309ce5b486f1639afa

python/SConscript

@@ -30,7 +30,7 @@ import os, os.path, re, sys
 
 Import('env')
 
-import m5scons
+import scons_helper
 
 def WriteEmbeddedPyFile(target, source, path, name, ext, filename):
     if isinstance(source, str):
@@ -151,7 +151,7 @@ def MakeDefinesPyFile(target, source, env):
     f = file(str(target[0]), 'w')
     print >>f, "import __main__"
     print >>f, "__main__.m5_build_env = ",
-    print >>f, m5scons.flatten_defines(env['CPPDEFINES'])
+    print >>f, scons_helper.flatten_defines(env['CPPDEFINES'])
     f.close()
 
 CFileCounter = 0

python/m5/objects/AlphaConsole.py

@@ -5,6 +5,5 @@ class AlphaConsole(PioDevice):
     type = 'AlphaConsole'
     cpu = Param.BaseCPU(Parent.any, "Processor")
     disk = Param.SimpleDisk("Simple Disk")
-    num_cpus = Param.Int(1, "Number of CPUs")
     sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
     system = Param.System(Parent.any, "system object")

python/m5/objects/BaseCPU.py

@@ -10,6 +10,7 @@ class BaseCPU(SimObject):
         itb = Param.AlphaITB("Instruction TLB")
         mem = Param.FunctionalMemory("memory")
         system = Param.System(Parent.any, "system object")
+        cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
 

python/m5/objects/Ethernet.py

@@ -64,7 +64,7 @@ class NSGigE(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    clock = Param.Clock('100MHz', "State machine processor frequency")
+    clock = Param.Clock('0ns', "State machine processor frequency")
 
     dma_data_free = Param.Bool(False, "DMA of Data is free")
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")