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Merge m5read@m5.eecs.umich.edu:/bk/m5

Browse Source 
into zamp.eecs.umich.edu:/.automount/fox/y/mserrano/m5_new/m5

--HG--
extra : convert_revision : bb3e977e79599c459fb32f309ce5b486f1639afa
This commit is contained in:
Miguel Serrano
2005-07-01 15:12:09 -04:00
parent 16a2357e86 efd0c5d4b0
commit 4f2480a18b
20 changed files with 339 additions and 129 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
dev/alpha_access.h
View File

@@ -33,12 +33,11 @@
* System Console Memory Mapped Register Definition
*/
#define ALPHA_ACCESS_VERSION (1301)
#define ALPHA_ACCESS_VERSION (1303)
#ifndef CONSOLE
#include <iosfwd>
#include <string>
class Checkpoint;
#ifdef CONSOLE
typedef unsigned uint32_t;
typedef unsigned long uint64_t;
#endif
// This structure hacked up from simos
@@ -71,11 +70,6 @@ struct AlphaAccess
uint64_t bootStrapImpure; // 70:
uint32_t bootStrapCPU; // 78:
uint32_t align2; // 7C: Dummy placeholder for alignment
#ifndef CONSOLE
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
#endif
};
#endif // __ALPHA_ACCESS_H__

32
dev/alpha_console.cc
View File

@@ -35,29 +35,28 @@
#include <string>
#include "base/inifile.hh"
#include "base/str.hh" // for to_number()
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "dev/alpha_console.hh"
#include "dev/simconsole.hh"
#include "dev/simple_disk.hh"
#include "dev/tsunami_io.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
#include "dev/tsunami_io.hh"
#include "sim/sim_object.hh"
#include "targetarch/byte_swap.hh"
#include "sim/system.hh"
using namespace std;
AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *p,
int num_cpus, MemoryController *mmu, Addr a,
MemoryController *mmu, Addr a,
HierParams *hier, Bus *bus)
: PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
{
@@ -69,11 +68,10 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
pioInterface->addAddrRange(RangeSize(addr, size));
}
alphaAccess = new AlphaAccess;
alphaAccess = new Access;
alphaAccess->last_offset = size - 1;
alphaAccess->version = ALPHA_ACCESS_VERSION;
alphaAccess->numCPUs = num_cpus;
alphaAccess->diskUnit = 1;
alphaAccess->diskCount = 0;
@@ -85,11 +83,14 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
alphaAccess->bootStrapImpure = 0;
alphaAccess->bootStrapCPU = 0;
alphaAccess->align2 = 0;
system->setAlphaAccess(addr);
}
void
AlphaConsole::init()
AlphaConsole::startup()
{
alphaAccess->numCPUs = system->getNumCPUs();
alphaAccess->kernStart = system->getKernelStart();
alphaAccess->kernEnd = system->getKernelEnd();
alphaAccess->entryPoint = system->getKernelEntry();
@@ -108,7 +109,8 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
switch (req->size)
{
case sizeof(uint32_t):
DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint32_t*)data);
DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
*(uint32_t*)data);
switch (daddr)
{
case offsetof(AlphaAccess, last_offset):
@@ -133,7 +135,8 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
}
break;
case sizeof(uint64_t):
DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint64_t*)data);
DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
*(uint64_t*)data);
switch (daddr)
{
case offsetof(AlphaAccess, inputChar):
@@ -266,7 +269,7 @@ AlphaConsole::cacheAccess(MemReqPtr &req)
}
void
AlphaAccess::serialize(ostream &os)
AlphaConsole::Access::serialize(ostream &os)
{
SERIALIZE_SCALAR(last_offset);
SERIALIZE_SCALAR(version);
@@ -289,7 +292,7 @@ AlphaAccess::serialize(ostream &os)
}
void
AlphaAccess::unserialize(Checkpoint *cp, const std::string &section)
AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(last_offset);
UNSERIALIZE_SCALAR(version);
@@ -327,7 +330,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
SimObjectParam<SimConsole *> sim_console;
SimObjectParam<SimpleDisk *> disk;
Param<int> num_cpus;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<System *> system;
@@ -343,7 +345,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
INIT_PARAM(sim_console, "The Simulator Console"),
INIT_PARAM(disk, "Simple Disk"),
INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(system, "system object"),
@@ -358,8 +359,7 @@ END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
CREATE_SIM_OBJECT(AlphaConsole)
{
return new AlphaConsole(getInstanceName(), sim_console, disk,
system, cpu, platform, num_cpus, mmu,
addr, hier, io_bus);
system, cpu, platform, mmu, addr, hier, io_bus);
}
REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)

12
dev/alpha_console.hh
View File

@@ -72,8 +72,14 @@ class SimpleDisk;
class AlphaConsole : public PioDevice
{
protected:
struct Access : public AlphaAccess
{
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
union {
AlphaAccess *alphaAccess;
Access *alphaAccess;
uint8_t *consoleData;
};
@@ -96,10 +102,10 @@ class AlphaConsole : public PioDevice
/** Standard Constructor */
AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *platform,
int num_cpus, MemoryController *mmu, Addr addr,
MemoryController *mmu, Addr addr,
HierParams *hier, Bus *bus);
virtual void init();
virtual void startup();
/**
* memory mapped reads and writes

7
dev/ide_atareg.h
View File

@@ -33,7 +33,14 @@
#ifndef _DEV_ATA_ATAREG_H_
#define _DEV_ATA_ATAREG_H_
#if defined(linux)
#include <endian.h>
#else
#include <machine/endian.h>
#endif
#define ATA_BYTE_ORDER LITTLE_ENDIAN
/*
* Drive parameter structure for ATA/ATAPI.
* Bit fields: WDC_* : common to ATA/ATAPI

2
dev/ide_ctrl.cc
View File

@@ -103,6 +103,8 @@ IdeController::IdeController(Params *p)
// setup the disks attached to controller
memset(disks, 0, sizeof(IdeDisk *) * 4);
dev[0] = 0;
dev[1] = 0;
if (params()->disks.size() > 3)
panic("IDE controllers support a maximum of 4 devices attached!\n");

70
dev/ns_gige.cc
View File

@@ -102,7 +102,7 @@ NSGigE::NSGigE(Params *p)
txDmaReadEvent(this), txDmaWriteEvent(this),
dmaDescFree(p->dma_desc_free), dmaDataFree(p->dma_data_free),
txDelay(p->tx_delay), rxDelay(p->rx_delay),
rxKickTick(0), txKickTick(0),
rxKickTick(0), rxKickEvent(this), txKickTick(0), txKickEvent(this),
txEvent(this), rxFilterEnable(p->rx_filter), acceptBroadcast(false),
acceptMulticast(false), acceptUnicast(false),
acceptPerfect(false), acceptArp(false),
@@ -841,7 +841,8 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("writing to read-only or reserved CFGR bits!\n");
regs.config |= reg & ~(CFGR_LNKSTS | CFGR_SPDSTS | CFGR_DUPSTS |
CFGR_RESERVED | CFGR_T64ADDR | CFGR_PCI64_DET);
CFGR_RESERVED | CFGR_T64ADDR |
CFGR_PCI64_DET);
// all these #if 0's are because i don't THINK the kernel needs to
// have these implemented. if there is a problem relating to one of
@@ -1487,13 +1488,19 @@ NSGigE::rxKick()
DPRINTF(EthernetSM, "receive kick rxState=%s (rxBuf.size=%d)\n",
NsRxStateStrings[rxState], rxFifo.size());
if (rxKickTick > curTick) {
DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
rxKickTick);
return;
next:
if (clock) {
if (rxKickTick > curTick) {
DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
rxKickTick);
goto exit;
}
// Go to the next state machine clock tick.
rxKickTick = curTick + cycles(1);
}
next:
switch(rxDmaState) {
case dmaReadWaiting:
if (doRxDmaRead())
@@ -1561,8 +1568,7 @@ NSGigE::rxKick()
if (rxDmaState != dmaIdle)
goto exit;
DPRINTF(EthernetDesc,
"rxDescCache: addr=%08x read descriptor\n",
DPRINTF(EthernetDesc, "rxDescCache: addr=%08x read descriptor\n",
regs.rxdp & 0x3fffffff);
DPRINTF(EthernetDesc,
"rxDescCache: link=%08x bufptr=%08x cmdsts=%08x extsts=%08x\n",
@@ -1783,7 +1789,6 @@ NSGigE::rxKick()
DPRINTF(EthernetSM, "entering next rxState=%s\n",
NsRxStateStrings[rxState]);
goto next;
exit:
@@ -1792,6 +1797,9 @@ NSGigE::rxKick()
*/
DPRINTF(EthernetSM, "rx state machine exited rxState=%s\n",
NsRxStateStrings[rxState]);
if (clock && !rxKickEvent.scheduled())
rxKickEvent.schedule(rxKickTick);
}
void
@@ -1954,13 +1962,18 @@ NSGigE::txKick()
DPRINTF(EthernetSM, "transmit kick txState=%s\n",
NsTxStateStrings[txState]);
if (txKickTick > curTick) {
DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
txKickTick);
return;
next:
if (clock) {
if (txKickTick > curTick) {
DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
txKickTick);
goto exit;
}
// Go to the next state machine clock tick.
txKickTick = curTick + cycles(1);
}
next:
switch(txDmaState) {
case dmaReadWaiting:
if (doTxDmaRead())
@@ -2022,6 +2035,8 @@ NSGigE::txKick()
if (txDmaState != dmaIdle)
goto exit;
DPRINTF(EthernetDesc, "txDescCache: addr=%08x read descriptor\n",
regs.txdp & 0x3fffffff);
DPRINTF(EthernetDesc,
"txDescCache: link=%08x bufptr=%08x cmdsts=%08x extsts=%08x\n",
txDescCache.link, txDescCache.bufptr, txDescCache.cmdsts,
@@ -2186,7 +2201,12 @@ NSGigE::txKick()
if (txDescCache.cmdsts & CMDSTS_INTR)
devIntrPost(ISR_TXDESC);
txState = txAdvance;
if (!txEnable) {
DPRINTF(EthernetSM, "halting TX state machine\n");
txState = txIdle;
goto exit;
} else
txState = txAdvance;
break;
case txAdvance:
@@ -2215,7 +2235,6 @@ NSGigE::txKick()
DPRINTF(EthernetSM, "entering next txState=%s\n",
NsTxStateStrings[txState]);
goto next;
exit:
@@ -2224,6 +2243,9 @@ NSGigE::txKick()
*/
DPRINTF(EthernetSM, "tx state machine exited txState=%s\n",
NsTxStateStrings[txState]);
if (clock && !txKickEvent.scheduled())
txKickEvent.schedule(txKickTick);
}
void
@@ -2429,6 +2451,7 @@ NSGigE::serialize(ostream &os)
SERIALIZE_SCALAR(rxDescCache.bufptr);
SERIALIZE_SCALAR(rxDescCache.cmdsts);
SERIALIZE_SCALAR(rxDescCache.extsts);
SERIALIZE_SCALAR(extstsEnable);
/*
* Serialize tx state machine
@@ -2441,6 +2464,7 @@ NSGigE::serialize(ostream &os)
SERIALIZE_SCALAR(txDescCnt);
int txDmaState = this->txDmaState;
SERIALIZE_SCALAR(txDmaState);
SERIALIZE_SCALAR(txKickTick);
/*
* Serialize rx state machine
@@ -2454,8 +2478,7 @@ NSGigE::serialize(ostream &os)
SERIALIZE_SCALAR(rxDescCnt);
int rxDmaState = this->rxDmaState;
SERIALIZE_SCALAR(rxDmaState);
SERIALIZE_SCALAR(extstsEnable);
SERIALIZE_SCALAR(rxKickTick);
/*
* If there's a pending transmit, store the time so we can
@@ -2575,6 +2598,7 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(rxDescCache.bufptr);
UNSERIALIZE_SCALAR(rxDescCache.cmdsts);
UNSERIALIZE_SCALAR(rxDescCache.extsts);
UNSERIALIZE_SCALAR(extstsEnable);
/*
* unserialize tx state machine
@@ -2589,6 +2613,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
int txDmaState;
UNSERIALIZE_SCALAR(txDmaState);
this->txDmaState = (DmaState) txDmaState;
UNSERIALIZE_SCALAR(txKickTick);
if (txKickTick)
txKickEvent.schedule(txKickTick);
/*
* unserialize rx state machine
@@ -2604,8 +2631,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
int rxDmaState;
UNSERIALIZE_SCALAR(rxDmaState);
this->rxDmaState = (DmaState) rxDmaState;
UNSERIALIZE_SCALAR(extstsEnable);
UNSERIALIZE_SCALAR(rxKickTick);
if (rxKickTick)
rxKickEvent.schedule(rxKickTick);
/*
* If there's a pending transmit, reschedule it now

2
dev/ns_gige.hh
View File

@@ -266,11 +266,13 @@ class NSGigE : public PciDev
Tick rxKickTick;
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
friend void RxKickEvent::process();
RxKickEvent rxKickEvent;
void txKick();
Tick txKickTick;
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
friend void TxKickEvent::process();
TxKickEvent txKickEvent;
/**
* Retransmit event