Merge ktlim@zamp:./local/clean/o3-merge/m5

into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d

src/sim/eventq.hh

@@ -46,6 +46,7 @@
 #include "sim/host.hh"	// for Tick
 
 #include "base/fast_alloc.hh"
+#include "base/misc.hh"
 #include "base/trace.hh"
 #include "sim/serialize.hh"
 
@@ -135,7 +136,7 @@ class Event : public Serializable, public FastAlloc
         /// same cycle (after unscheduling the old CPU's tick event).
         /// The switch needs to come before any tick events to make
         /// sure we don't tick both CPUs in the same cycle.
-        CPU_Switch_Pri		=   31,
+        CPU_Switch_Pri		=   -31,
 
         /// Serailization needs to occur before tick events also, so
         /// that a serialize/unserialize is identical to an on-line
@@ -351,7 +352,8 @@ inline void
 Event::schedule(Tick t)
 {
     assert(!scheduled());
-    assert(t >= curTick);
+//    if (t < curTick)
+//        warn("t is less than curTick, ensure you don't want cycles");
 
     setFlags(Scheduled);
 #if TRACING_ON

src/sim/pseudo_inst.cc

@@ -148,6 +148,54 @@ namespace AlphaPseudo
         exitSimLoop(when, "m5_exit instruction encountered");
     }
 
+    void
+    loadsymbol(ExecContext *xc)
+    {
+        const string &filename = xc->getCpuPtr()->system->params()->symbolfile;
+        if (filename.empty()) {
+            return;
+        }
+
+        std::string buffer;
+        ifstream file(filename.c_str());
+
+        if (!file)
+            fatal("file error: Can't open symbol table file %s\n", filename);
+
+        while (!file.eof()) {
+            getline(file, buffer);
+
+            if (buffer.empty())
+                continue;
+
+            int idx = buffer.find(' ');
+            if (idx == string::npos)
+                continue;
+
+            string address = "0x" + buffer.substr(0, idx);
+            eat_white(address);
+            if (address.empty())
+                continue;
+
+            // Skip over letter and space
+            string symbol = buffer.substr(idx + 3);
+            eat_white(symbol);
+            if (symbol.empty())
+                continue;
+
+            Addr addr;
+            if (!to_number(address, addr))
+                continue;
+
+            if (!xc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
+                continue;
+
+
+            DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
+        }
+        file.close();
+    }
+
     void
     resetstats(ThreadContext *tc, Tick delay, Tick period)
     {

src/sim/pseudo_inst.hh

@@ -51,6 +51,7 @@ namespace AlphaPseudo
     void ivle(ThreadContext *tc);
     void m5exit(ThreadContext *tc, Tick delay);
     void m5exit_old(ThreadContext *tc);
+    void loadsymbol(ThreadContext *xc);
     void resetstats(ThreadContext *tc, Tick delay, Tick period);
     void dumpstats(ThreadContext *tc, Tick delay, Tick period);
     void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);

src/sim/serialize.cc

@@ -52,6 +52,9 @@
 #include "sim/sim_exit.hh"
 #include "sim/sim_object.hh"
 
+// For stat reset hack
+#include "sim/stat_control.hh"
+
 using namespace std;
 
 int Serializable::ckptMaxCount = 0;
@@ -404,3 +407,36 @@ Checkpoint::sectionExists(const std::string &section)
 {
     return db->sectionExists(section);
 }
+
+/** Hacked stat reset event */
+
+class StatresetParamContext : public ParamContext
+{
+  public:
+    StatresetParamContext(const string &section);
+    ~StatresetParamContext();
+    void startup();
+};
+
+StatresetParamContext statParams("statsreset");
+
+Param<Tick> reset_cycle(&statParams, "reset_cycle",
+                        "Cycle to reset stats on", 0);
+
+StatresetParamContext::StatresetParamContext(const string &section)
+    : ParamContext(section)
+{ }
+
+StatresetParamContext::~StatresetParamContext()
+{
+}
+
+void
+StatresetParamContext::startup()
+{
+    if (reset_cycle > 0) {
+        Stats::SetupEvent(Stats::Reset, curTick + reset_cycle, 0);
+        cprintf("Stats reset event scheduled for %lli\n",
+                curTick + reset_cycle);
+    }
+}

src/sim/stat_control.cc

@@ -160,13 +160,13 @@ class StatEvent : public Event
     Tick repeat;
 
   public:
-    StatEvent(int _flags, Tick _when, Tick _repeat);
+    StatEvent(EventQueue *queue, int _flags, Tick _when, Tick _repeat);
     virtual void process();
     virtual const char *description();
 };
 
-StatEvent::StatEvent(int _flags, Tick _when, Tick _repeat)
-    : Event(&mainEventQueue, Stat_Event_Pri),
+StatEvent::StatEvent(EventQueue *queue, int _flags, Tick _when, Tick _repeat)
+    : Event(queue, Stat_Event_Pri),
       flags(_flags), repeat(_repeat)
 {
     setFlags(AutoDelete);
@@ -185,8 +185,10 @@ StatEvent::process()
     if (flags & Stats::Dump)
         DumpNow();
 
-    if (flags & Stats::Reset)
+    if (flags & Stats::Reset) {
+        cprintf("Resetting stats!\n");
         reset();
+    }
 
     if (repeat)
         schedule(curTick + repeat);
@@ -214,9 +216,12 @@ DumpNow()
 }
 
 void
-SetupEvent(int flags, Tick when, Tick repeat)
+SetupEvent(int flags, Tick when, Tick repeat, EventQueue *queue)
 {
-    new StatEvent(flags, when, repeat);
+    if (queue == NULL)
+        queue = &mainEventQueue;
+
+    new StatEvent(queue, flags, when, repeat);
 }
 
 /* namespace Stats */ }

src/sim/stat_control.hh

@@ -34,6 +34,8 @@
 #include <fstream>
 #include <list>
 
+class EventQueue;
+
 namespace Stats {
 
 enum {
@@ -45,7 +47,7 @@ class Output;
 extern std::list<Output *> OutputList;
 
 void DumpNow();
-void SetupEvent(int flags, Tick when, Tick repeat = 0);
+void SetupEvent(int flags, Tick when, Tick repeat = 0, EventQueue *queue = NULL);
 
 void InitSimStats();
 

src/sim/system.hh

@@ -182,6 +182,7 @@ class System : public SimObject
 
         std::string kernel_path;
         std::string readfile;
+        std::string symbolfile;
 #endif
     };